Flash backed dram module including logic for isolating the dram

Abstract

A memory device for use with a primary power source including: non-volatile memory; volatile memory; an interface for connecting to a backup power source; isolation logic for controlling access to the volatile memory by a host processor, said isolation logic having a first mode during which the isolation logic provides the host processor with access to the volatile memory for storing or reading data and a second mode during which the isolation logic isolates the volatile memory from access by the host processor; and a controller controlling the isolation logic, said controller programmed to place the isolation logic in the first mode when the volatile memory is being powered by the primary power source and, when power to the volatile memory from the primary power source is interrupted, to place the isolation logic in the second mode and transfer data from the volatile memory to the non-volatile memory.

1 . A memory device for use with a host processor and a primary power source, the memory device comprising:
 non-volatile memory;   volatile memory;   an interface for connecting to a backup power source arranged to temporarily power the volatile memory upon a loss of power from the primary power source;   isolation logic for controlling access to the volatile memory by the host processor, said isolation logic having a first mode during which the isolation logic provides the host processor with access to the volatile memory for storing or reading data and a second mode during which the isolation logic isolates the volatile memory from access by the host processor; and   a controller controlling the isolation logic, said controller programmed to place the isolation logic in the first mode when the volatile memory is being powered by the primary power source and, when power to the volatile memory from the primary power source is interrupted, to place the isolation logic in the second mode and transfer data from the volatile memory to the non-volatile memory.   
     
     
         2 . The memory device of  claim 1 , wherein the controller is further programmed to: restore data from the non-volatile memory to the volatile memory upon a restoration of the primary power source; and
 when the data is restored, place the isolation logic in the first mode.   
     
     
         3 . The memory device of  claim 1 , wherein the controller is further programmed to drive a coupling between the controller and the isolation logic to a high impedance state when the isolation logic is in the first mode. 
     
     
         4 . The memory device of  claim 1 , wherein in the isolation logic comprises at least one multiplexer. 
     
     
         5 . The memory device of  claim 1 , wherein the volatile memory comprises a dynamic random access memory. 
     
     
         6 . The memory device of  claim 1 , wherein the non-volatile memory comprises electrically erasable programmable read-only memories (EEPROMs). 
     
     
         7 . The memory device of  claim 1 , wherein the controller comprises at least one of an application-specific integrated circuit (ASIC) and a field programmable gate array (FPGA). 
     
     
         8 . The memory device of  claim 1 , wherein power from the backup power source is primarily from a capacitor. 
     
     
         9 . The memory device of  claim 1 , wherein power from the backup power source is primarily from a super capacitor. 
     
     
         10 . A method comprising:
 detecting a power failure of a primary power source of a volatile memory; and   in response to detecting the power failure and while the volatile memory is powered by a backup power source:   changing a mode of isolation logic from a first mode that provides a host processor with access to the volatile memory for storing or reading data when the volatile memory is being powered by the primary power source to a second mode that isolates the volatile memory from access by the host processor; and   moving data stored in the volatile memory to a non-volatile memory.   
     
     
         11 . The method of  claim 10 , further comprising:
 restoring data from the non-volatile memory to the volatile memory upon a restoration of the primary power source; and   when the data is restored, placing the isolation logic in the first mode.   
     
     
         12 . The method of  claim 10 , further comprising drive a coupling between the controller and the isolation logic to a high impedance state when the isolation logic is in the first mode. 
     
     
         13 . The method of  claim 10 , wherein in the isolation logic comprises at least one multiplexer. 
     
     
         14 . The method of  claim 10 , wherein the volatile memory comprises a dynamic random access memory. 
     
     
         15 . The method of  claim 10 , wherein the non-volatile memory comprises electrically erasable programmable read-only memories (EEPROMs). 
     
     
         16 . The method of  claim 10 , wherein power from the backup power source is primarily from a capacitor. 
     
     
         17 . The method of  claim 10 , wherein power from the backup power source is primarily from a super capacitor.