US2012202342A1PendingUtilityA1

Semiconductor device and manufacturing method thereof

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Assignee: NAKAJIMA KOUJIPriority: Oct 16, 2008Filed: Apr 18, 2012Published: Aug 9, 2012
Est. expiryOct 16, 2028(~2.3 yrs left)· nominal 20-yr term from priority
Inventors:Kouji Nakajima
H10D 30/66H10D 64/662H10D 64/519H10D 62/393H10D 84/0149H10D 84/038H10D 30/668H10D 30/665H10D 30/0291
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Claims

Abstract

A method of manufacturing a semiconductor device includes depositing a wiring metal layer on a photoresist layer and a portion of a first layer of a gate lead-out electrode which is exposed via an opening, lifting-off a wiring metal layer formed on the photoresist layer forming an interlayer insulation film over the entire surface including the first layer and the wiring metal layer, selectively removing the interlayer insulation film thereby forming a contact via reaching a source region formed in a cell region, and forming a source electrode on the interlayer insulation film and electrically connecting a source electrode with the source region.

Claims

exact text as granted — not AI-modified
1 . A method of manufacturing a semiconductor device including a cell region in which a plurality of transistor cells are arranged, a gate electrode, and a gate lead-out electrode formed in a gate finger region different from the region where the cell region is formed, the method comprising:
 (a) forming a gate electrode and a first layer of a gate lead-out electrode with a first conductive material above a semiconductor layer;   (b) forming a photoresist layer over the entire surface above the gate electrode and the first layer;   (c) forming an opening in the photoresist layer so that a portion of the first layer of the gate lead-out electrode is exposed;   (d) depositing a wiring metal layer on the photoresist layer and the portion of the first layer of the gate lead-out electrode which is exposed via the opening;   (e) lifting-off the wiring metal layer formed on the photoresist layer with the photoresist layer;   (f) forming an interlayer insulation film over the entire surface including the first layer and the wiring metal layer;   (g) selectively removing the interlayer insulation film thereby forming a contact via reaching the source region formed in the cell region; and   (h) forming a source electrode on the interlayer insulation film and electrically connecting the source electrode with the source region.   
     
     
         2 . The method of manufacturing the semiconductor device according to  claim 1 , wherein
 the lowermost layer of the wiring metal layer comprises an adhesion metal layer.   
     
     
         3 . The method of manufacturing the semiconductor device according to  claim 2 , wherein
 the adhesion metal layer comprises a titanium film and a titanium nitride film deposited in this order.   
     
     
         4 . The method of manufacturing the semiconductor device according to  claim 1 , wherein
 the first conductive material comprises a polysilicon.   
     
     
         5 . The method of manufacturing the semiconductor device according to  claim 1 , wherein
 the wiring metal layer comprises at least one of aluminum, copper, and tungsten.   
     
     
         6 . The method of manufacturing the semiconductor device according to  claim 1 , wherein
 the source electrode is formed over the entire surface above the cell region and the gate lead-out electrode when viewed in a plane.   
     
     
         7 . The method of manufacturing a semiconductor device according to  claim 1 , wherein
 the interlayer insulation film comprises a laminate film made of a plurality of different materials.   
     
     
         8 . The method of manufacturing a semiconductor device according to  claim 7 , wherein
 the interlayer insulation film comprises a non-doped silicate glass film and a boron-phosphorus silicate glass film formed in a layer thereabove.

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