System and apparatus for group floating-point arithmetic operations

Abstract

Systems and apparatuses are presented relating a programmable processor comprising an execution unit that is operable to decode and execute instructions received from an instruction path and partition data stored in registers in the register file into multiple data elements, the execution unit capable of executing group data handling operations that re-arrange data elements in different ways in response to data handling instructions, the execution unit further capable of executing a plurality of different group floating-point and group integer arithmetic operations that each arithmetically operates on the multiple data elements stored in registers in the register file to produce a catenated result that is returned to a register in the register file, wherein the catenated result comprises a plurality of individual results.

1 - 9 . (canceled) 
     
     
         10 . A programmable processor comprising:
 (a) an instruction path and a data path;   (b) an external interface operable to receive data from an external source and communicate the received data over the data path;   (c) a register file comprising a plurality of registers coupled to the data path; and   (d) an execution unit, coupled to the instruction and data paths, that is operable to   decode and execute instructions received from the instruction path and partition data stored in registers in the register file into multiple data elements, the execution unit capable of executing group data handling operations that re-arrange data elements in different ways in response to data handling instructions, the execution unit further capable of executing a plurality of different group floating-point and group integer arithmetic operations that each arithmetically operates on the multiple data elements stored in registers in the register file to produce a catenated result that is returned to a register in the register file, wherein the catenated result comprises a plurality of individual results,   wherein the execution unit is capable of executing first, second, and third group multiply instructions, each of which
 (i) partitions data in first and second registers in the register file into a first plurality and a second plurality of equal-sized data elements, 
 (ii) multiplies each data element in the first register with a corresponding data element in the second register to produce the plurality of individual results, which are equal in size to one another, 
 (iii) provides the plurality of individual results as the catenated result 
   wherein the first group multiply instruction operates on data elements of 8-bit integer data and produces data elements of 16-bit integer data, the second group multiply instruction operates on data elements of 16-bit integer data and produces data elements of 32-bit integer data, and the third group multiply instruction operates on data elements of 32-bit floating-point data and produces data elements of 32-bit floating-point data.   
     
     
         11 . The programmable processor of  claim 10  wherein the execution unit is further capable of executing first, second, third, and fourth group add instructions, each of which
 (i) partitions data in first and second registers in the register file into a first plurality and a second plurality of equal-sized data elements, 
 (ii) adds each data element in the first register with a corresponding data element in the second register to produce the plurality of individual results, which are equal in size to one another, and 
 (iii) provides the plurality of individual results as the catenated result, 
 wherein the first group add instruction operates on data elements of 8-bit integer data, the second group add instruction operates on data elements of 16-bit integer data, the third group add instruction operates on data elements of 32-bit integer data, and the fourth group add instruction operates on data elements of 32-bit floating-point data. 
 
     
     
         12 - 20 . (canceled) 
     
     
         21 . A data processing system comprising:
 (a) an instruction path and a data path;   (b) an external interface operable to receive data from an external source and communicate the received data over the data path;   (c) a register file comprising a plurality of registers coupled to the data path; and   (d) an execution unit, coupled to the instruction and data paths, that is operable to decode and execute instructions received from the instruction path and partition data stored in registers in the register file into multiple data elements, the execution unit capable of executing group data handling operations that re-arrange data elements in different ways in response to data handling instructions, the execution unit further capable of executing a plurality of different group floating-point and group integer arithmetic operations that each arithmetically operates on the multiple data elements stored in registers in the register file to produce a catenated result that is returned to a register in the register file, wherein the catenated result comprises a plurality of individual results,   wherein the execution unit is capable of executing first, second, and third group multiply instructions, each of which
 (i) partitions data in first and second registers in the register file into a first plurality and a second plurality of equal-sized data elements, 
 (ii) multiplies each data element in the first register with a corresponding data element in the second register to produce the plurality of individual results, which are equal in size to one another, 
 (iii) provides the plurality of individual results as the catenated result, 
   wherein the first group multiply instruction operates on data elements of 8-bit integer data and produces data elements of 16-bit integer data, the second group multiply instruction operates on data elements of 16-bit integer data and produces data elements of 32-bit integer data, and the third group multiply instruction operates on data elements of 32-bit floating-point data and produces data elements of 32-bit floating-point data.   
     
     
         22 . The data processing system of  claim 21  wherein the execution unit is further capable of executing first, second, third, and fourth group add instructions, each of which
 (i) partitions data in first and second registers in the register file into a first plurality and a second plurality of equal-sized data elements, 
 (ii) adds each data element in the first register with a corresponding data element in the second register to produce the plurality of individual results, which are equal in size to one another, and 
 (iii) provides the plurality of individual results as the catenated result, 
 wherein the first group add instruction operates on data elements of 8-bit integer data, the second group add instruction operates on data elements of 16-bit integer data, the third group add instruction operates on data elements of 32-bit integer data, and the fourth group add instruction operates on data elements of 32-bit floating-point data.