Semiconductor memory apparatus and method of testing the same

Abstract

A method of testing a semiconductor memory apparatus is provided. The data alignment units other than the one data align unit being tested are deactivated. Serial data is input to the activated data alignment unit to generate parallel data. The parallel data is decoded. A test mode signal corresponding to the decoded result is enabled to perform the test. Different serial data is input where the test mode signal is enabled to generate and decode parallel data. Both tests are then performed simultaneously based on a test mode signal corresponding to a result of the decoded parallel data.

1 . A method of testing a semiconductor memory apparatus, comprising:
 a) deactivating operations of data alignment units other than one data alignment unit upon testing;   b) generating parallel data by inputting serial data to the activated data alignment unit and decoding the parallel data;   c) performing a test by enabling a test mode signal corresponding to the decoded result;   d) generating and decoding parallel data by inputting serial data different from the serial data in the state where the enabled test mode signal is maintained; and   e) simultaneously performing a test defined at c) and a test defined at d) by enabling a test mode signal corresponding to a result decoded at d).   
     
     
         2 . The method of testing a semiconductor memory apparatus of  claim 1 , wherein the a) includes:
 enabling a test enable signal in response to a test mode setting signal; and   activating one data alignment unit in response to the test enable signal and deactivating other data alignment units.   
     
     
         3 . The method of testing a semiconductor memory apparatus of  claim 1 , wherein each of the data alignment units is configured to align the serial data received from the outside as the parallel data by the semiconductor memory apparatus. 
     
     
         4 . The method of testing a semiconductor memory apparatus of  claim 1 , wherein c) further includes disabling the enabled test mode signal when a reset signal is enabled. 
     
     
         5 . The method of testing a semiconductor memory apparatus of  claim 1 , further comprising f) ending a test by inputting a read command when a test is completed, after e).