Test point design for a high speed bus

Abstract

A test point design comprising: a circuit board comprising a plurality of layers including a power plane and a ground plane, the circuit board further comprises a differential pair of signal lines including a first signal line and a second signal line; and a pair of test point pads including a first test point pad connected to the first signal line and a second test point pad connected to the second signal line, wherein a first portion of the power plane and a first portion of the ground plane below the first test point pad are removed and a second portion of the power plane and a second portion of the ground plane below the second test point pad are removed.

1 - 11 . (canceled) 
     
     
         12 . A method of configuring a test point design for a circuit board including a power plane and a ground plane, the method comprising;
 a. removing a first portion of the power plane from a first position on the power plane that is to be aligned with a first test point pad on an outer layer of the circuit board;   b. removing a second portion of the power plane from a second position on the power plane that is to be aligned with a second test point pad on the outer layer of the circuit board;   c. removing a first portion of the ground plane from a first position on the ground plane that is to be aligned with the first test point pad, wherein the first position on the ground plane is aligned with the first position on the power plane;   d. removing a second portion of the ground plane from a second position on the ground plane that is to be aligned with the second test point pad, wherein the second position on the ground plane is aligned with the second position on the power plane;   e. adding a pair of differential signal lines to the outer layer of the circuit board, wherein the pair of differential signal lines includes a first signal line and a second signal line; and   f. adding the first test point pad and the second test point pad to the outer layer of the circuit board, wherein the first test point pad is connected to the first signal line and the second test point pad is connected to the second signal line.   
     
     
         13 . The method of  claim 12  further comprising staggering a position of the first test point pad and a position of the second test point pad relative to the pair of signal lines. 
     
     
         14 . The method of  claim 13  wherein the first test point pad and the second test point pad are staggered such that a first perpendicular line between a center of the first test point pad and the first signal line is not aligned with a second perpendicular line between a center of the second test point pad and the second signal line. 
     
     
         15 . The method of  claim 13  wherein the pitch between the center of the first test point pad and the center of the second test point pad is about  65  millimeters. 
     
     
         16 . The method of  claim 13  wherein the pair of test point pads are staggered by a pitch sufficient to enable a first probe to contact the first test point pad and a second probe to contact the second test point pad concurrently. 
     
     
         17 . The method of  claim 13  wherein the differential signal lines are positioned adjacent to each other. 
     
     
         18 . The method of  claim 12  wherein a segment of the first signal line connected to the first test pad, a segment of the second signal line connected to the second test pad, the first test pad, and the second test pad are all positioned in a same plane. 
     
     
         19 . The method of  claim 12  wherein the circuit board comprises a plurality of power planes, and the first portion and the second portion from one or more of the plurality of power planes nearest the outer layer are removed. 
     
     
         20 . The method of  claim 12  wherein the circuit board comprises a plurality of ground planes, and the first portion and the second portion from one or more of the plurality of ground planes nearest the outer layer are removed. 
     
     
         21 . The method of  claim 12  wherein the circuit board comprises a plurality of power planes and a plurality of ground planes, and the first portion and the second portion from one or more of the plurality of power planes and one or more of the plurality of ground planes nearest the outer layer are removed. 
     
     
         22 . The method of  claim 12  wherein the circuit board comprises a plurality of layers including the power plane, the ground plane, and the outer layer, further wherein each layer is formed using semiconductor processing techniques and the first portions and second portions of each of the power plane and the ground plane are removed by selective etching. 
     
     
         23 . The method of  claim 22  wherein the removed first portion and second portion of the power plane are filled by insulating material from an insulating layer deposited over the power plane, and the removed first portion and second portion of the ground plane are filled by insulating material from an insulating layer deposited over the ground plane. 
     
     
         24 . The method of  claim 12  wherein the circuit board comprises a plurality of layers including the power plane, the ground plane, and the outer layer, the method further comprises:
 a. separately forming at least the power plane as part of a first layered structure and the ground plane as part of a second layered structure; 
 b. coupling the first layered structure to the second layered structure to form a combined layer structure; 
 c. cutting a first block and a second block from the combined layer structure, wherein a position of the first block corresponds to the first position on the ground plane and the first position on the power plane, and a position of the second block corresponds to the second position on the ground plane and the second position on the power plane; and 
 d. coupling the outer layer to the combined layer structure so that the first test point pad is aligned with the first block and the second test point pad is aligned with the second block. 
 
     
     
         25 . The method of  claim 24  wherein the pair of differential signal lines, the first test point pad, and the second test point pad are formed on the outer layer prior to coupling the outer layer to the combined layer structure. 
     
     
         26 . The method of  claim 24  wherein the outer layer is coupled to the combined layer structure prior to forming the pair of differential signal lines, the first test point pad, and the second test point pad on the outer layer, and once coupled to the combined layer structure, the pair of differential signal lines, the first test point pad, and the second test point pad are formed on the outer layer.