Semiconductor device including capacitor and double-layer metal contact and fabrication method thereof

Abstract

Disclosed are a semiconductor device comprising a capacitor and a double-layer metal contact and a method fabricating the same. The method comprising: forming a gate of a peripheral transistor for a peripheral circuit; forming a first contact and a first peripheral circuit wiring layer pattern on a first interlayer insulating layer; forming a second contact and a second peripheral circuit wiring layer pattern; selectively removing a portion of the second interlayer insulating layer in a cell region; forming a mold layer covering the second peripheral circuit wiring layer pattern; forming storage nodes passing through the mold layer; removing the mold layer; forming a dielectric layer and a plate node, which cover the storage nodes; forming a third interlayer insulating layer; and forming third contacts passing through the third interlayer insulating layer.

1 . A method for fabricating a semiconductor device comprising a capacitor and a double-layer metal contact, the method comprising:
 forming a second interlayer insulating layer on a cell region and a peripheral region;   forming a second contact which passes through a portion of the second interlayer insulating layer on the peripheral region;   selectively removing a portion of the second interlayer insulating layer on the cell region while allowing a portion of the second interlayer insulating layer on the peripheral region to remain;   forming a mold layer covering both the portion of the cell region from which the second interlayer insulating layer was removed and the second contact;   forming storage nodes which pass through a portion of the mold layer in the cell region;   selectively removing the mold layer to expose the storage nodes;   forming a dielectric layer and a plate node, which cover the exposed storage nodes;   forming a third interlayer insulating layer covering the plate node; and   forming third contacts which pass through the third interlayer insulating layer so as to be connected to the plate node and the second contact, respectively.   
     
     
         2 . The method of  claim 1 , wherein the method further comprises:
 forming a gate for a peripheral circuit on the peripheral region;   forming a first interlayer insulating layer covering the gate;   forming bit lines which are insulated by the portion of the first interlayer insulating layer on the cell region;   forming storage node contacts which pass through the first interlayer insulating layer so as to be connected to the storage nodes, respectively; and   forming on the portion of the first interlayer insulating layer on the peripheral region a first contact which connects the second contact to the gate.   
     
     
         3 . The method of  claim 1 , wherein selectively removing the portion of the second interlayer insulating layer on the cell region comprises:
 forming on the second interlayer insulating layer a mask pattern for exposing the cell region; and   selectively etching out a portion of the second interlayer insulating layer exposed through the mask pattern.   
     
     
         4 . The method of  claim 1 , wherein the method further comprises:
 forming at an interface between the mold layer and the remaining second interlayer insulating layer an etch stopper extending to cover the second peripheral circuit wiring layer pattern, in which the etch stopper protects the second interlayer insulating layer when the mold layer is removed.   
     
     
         5 . The method of  claim 4 , wherein forming the dielectric layer and the plate node comprises:
 forming layers for the dielectric layer and the plate node so as to extend onto the etch stopper; and   selectively etching out a portion of the dielectric layer for the plate node, which overlaps with the remaining portion of the second interlayer insulating layer, thus patterning the plate node,   in which the third contacts which are connected to the plate node are located on the remaining portion of the second interlayer insulating portion.   
     
     
         6 . The method of  claim 1 , wherein the method further comprises:
 forming on the mold layer a support layer for supporting the storage nodes.   
     
     
         7 . A method for fabricating a semiconductor device comprising a capacitor and a double-layer metal contact, the method comprising:
 forming a gate of a peripheral transistor for a peripheral circuit on a peripheral region of a semiconductor substrate including a cell region and the peripheral region;   forming a first interlayer insulating layer covering the gate;   forming a first contact and a first peripheral circuit wiring layer pattern, which are connected to the gate so as to constitute the peripheral circuit;   forming a second interlayer insulating layer covering the first peripheral circuit wiring layer pattern;   forming a second contact and a second peripheral circuit wiring layer pattern, which pass through the second interlayer insulating layer so as to constitute the peripheral circuit;   selectively removing a portion of the second interlayer insulating layer on the cell region while allowing a portion of the second interlayer insulating layer on the peripheral region to remain;   forming a mold layer covering both a portion of the semiconductor substrate from which the portion of the second interlayer insulating layer was removed and the second peripheral circuit wiring layer pattern;   forming storage nodes that pass through a portion of the mold layer in the cell region;   selectively removing the mold layer to expose the storage nodes;   forming a dielectric layer and a plate node, which cover the exposed storage nodes;   forming a third interlayer insulating layer covering the plate node; and   forming third contacts that pass through the third interlayer insulating layer so as to be connected to the plate node and the second peripheral circuit wiring layer pattern, respectively.   
     
     
         8 . The method of  claim 7 , wherein the peripheral circuit comprises a sense amplifier that senses data to be stored in the storage nodes. 
     
     
         9 . The method of  claim 7 , wherein the method further comprises:
 forming bit lines which are insulated by a portion of the first interlayer insulating layer on the cell region;   forming storage node contacts which pass through the first interlayer insulating layer so as to be connected to the storage nodes, respectively.   
     
     
         10 . The method of  claim 9 , wherein forming the bit lines comprises:
 forming damascene trenches in the first interlayer insulating layer; and   forming the bit lines filling the damascene trenches.   
     
     
         11 . The method of  claim 7 , wherein forming the first peripheral circuit wiring layer pattern comprises:
 obtaining a layout of the peripheral circuit wiring line for the peripheral circuit;   extracting a layout of the first peripheral circuit wiring layer pattern, a layout of the second contact and a layout of the second peripheral circuit from the layout of the peripheral circuit wiring line;   forming a first contact hole exposing the gate; forming the first peripheral circuit wiring layer, which fills the first contact hole, on the first interlayer insulating layer; and   selectively etching the first circuit wiring layer so as to have a configuration corresponding to the layout of the first peripheral circuit wiring layer pattern, thus forming the first contact and the first peripheral circuit wiring layer pattern.   
     
     
         12 . The method of  claim 7 , wherein forming the second peripheral circuit wiring layer pattern comprises:
 forming the second contact hole, which passes through the second interlayer insulating layer, so as to have a configuration corresponding to the layout of the second contact;   forming the second peripheral circuit wiring layer, which fills the second contact hole, on the second interlayer insulating layer; and   selectively etching the second peripheral circuit wiring layer so as to have a configuration corresponding to the layout of the second peripheral circuit wiring layer pattern, thus forming the second contact and the second peripheral circuit wiring layer pattern.   
     
     
         13 . The method of  claim 7 , wherein selectively removing the portion of the second interlayer insulating layer on the cell region comprises:
 forming on the second interlayer insulating layer a mask pattern for exposing the cell region; and   selectively etching out a portion of the second interlayer insulating layer exposed through the mask pattern.   
     
     
         14 . The method of  claim 7 , wherein the method further comprises:
 forming at an interface between the mold layer and the remaining second interlayer insulating layer an etch stopper extending to cover the second peripheral circuit wiring layer pattern, in which the etch stopper protects the second interlayer insulating layer when the mold layer is removed.   
     
     
         15 . The method of  claim 14 , wherein the forming the dielectric layer and the plate node comprises:
 forming layers for the dielectric layer and the plate node so as to extend onto the etch stopper exposed by removal of the mold layer; and   selectively etching out a portion of the dielectric layer for the plate node, which overlaps with the remaining portion of the second interlayer insulating layer, thus patterning the plate node,   in which the third contacts which are connected to the plate node are located on the remaining portion of the second interlayer insulating portion.   
     
     
         16 . The method of  claim 7 , wherein the method further comprises:
 forming on the mold layer a support layer for supporting the storage nodes.   
     
     
         17 . A semiconductor device comprising:
 a cell region and a peripheral region;   storage nodes formed in the cell region;   a second contact passing through a second interlayer insulating layer formed on the peripheral region;   a dielectric layer and a plate node, which cover the storage node and of which the end extends onto the second interlayer insulating layer;   a third interlayer insulating layer covering the plate node and the second interlayer insulating layer;   and third contacts which pass through the second interlayer insulating layer so as to be connected to both a portion of the plate node on the second interlayer insulating layer and the second contact, respectively.   
     
     
         18 . The semiconductor device of  claim 17 , wherein the semiconductor device further comprises:
 a gate of a peripheral transistor formed on the peripheral region to constitute a peripheral circuit;   a first interlayer insulating layer covering the gate;   bit lines insulated by a portion of the first interlayer insulating layer on the cell region;   storage node contacts which pass through the first interlayer insulating layer so as to be connected to the storage nodes, respectively; and   a first contact which passes through a portion of the first interlayer insulating layer on the peripheral region to connect the second contact to the gate.   
     
     
         19 . The semiconductor device of  claim 18 , wherein the semiconductor device further comprises an etch stopper formed at an interface between the second and third interlayer insulating layers and extending onto the first interlayer insulating layer to support sides of the lower portion of the storage nodes and to isolate the storage nodes from the third interlayer insulating layer. 
     
     
         20 . The semiconductor device of  claim 17 , wherein the semiconductor device further comprises a support layer which supports the upper portion of the storage nodes, where the storage nodes are formed in a pillar shape. 
     
     
         21 . A semiconductor device:
 a semiconductor substrate including a cell region and a peripheral region;   a peripheral transistor and a gate, which are formed on the peripheral region of the semiconductor substrate to constitute a peripheral region;   a first interlayer insulating layer formed to cover the gate;   a first contact and a first peripheral circuit wiring layer pattern, which are formed on a portion of the first interlayer insulating layer on the peripheral region so as to be connected to the gate and to constitute the peripheral circuit;   a second interlayer insulating layer formed on the peripheral region to cover the first peripheral circuit wiring layer pattern;   a second contact and a second peripheral circuit wiring layer pattern, which are formed to pass through the second interlayer insulating layer so as to constitute the peripheral circuit;   storage nodes formed on a portion of the first interlayer insulating layer in the cell region;   a dielectric layer and a plate node, which cover the storage nodes and of which the end extends onto the second interlayer insulating layer;   a third interlayer insulating layer covering the plate node and the second interlayer insulating layer; and   third contacts which pass through the second interlayer insulating layer so as to be connected to both a portion of the plate node on the second interlayer insulating layer and the second peripheral circuit wiring layer pattern, respectively.   
     
     
         22 . The semiconductor device of  claim 21 , wherein the peripheral circuit comprises a sense amplifier which senses data to be stored in the storage nodes. 
     
     
         23 . The semiconductor device of  claim 21 , wherein the semiconductor device further comprises:
 bit lines insulated by the portion of the first interlayer insulating layer in the cell region; and   storage node contacts which pass through the first interlayer insulating layer so as to be connected to the storage nodes, respectively.   
     
     
         24 . The semiconductor device of  claim 21 , wherein the semiconductor device further comprises an etch stopper formed at an interface between the second and third interlayer insulating layers and extending onto the first interlayer insulating layer to support the sides of a lower portion of the storage nodes and to isolate the storage nodes from the third interlayer insulating layer. 
     
     
         25 . The semiconductor device of  claim 21 , wherein the semiconductor device further comprises a support layer which supports an upper portion of the storage nodes. 
     
     
         26 . The semiconductor device of  claim 21 , wherein the height of the second contact is 45-70% of the height of the storage node.