Shift Register

Abstract

A shift register comprises many stages, and each of stages comprises a first, a second and a third level control unit and a first and a second control unit is provided. The first and the second level control unit respectively provides a first clock signal and a voltage to an output terminal. The first driving unit and the level control unit are coupled to a first node. The first driving unit turns on and turns off the first level control unit in response to an input signal, a second control signal and a first control signal of the next stage. The second driving unit turns on and turns off the second level control unit in response to the first control signal. The third level control unit provides a first voltage to the output terminal in response to the second control signal and the first control signal.

1 . A shift register having a plurality of stages provided on two sides of a display panel for providing scan signals , wherein each stage of the shift register on one side of the display panel comprises:
 a first level control unit for providing a first clock signal to an output terminal;   a first driving unit coupled to an input terminal of the first level control unit via a first node for providing a first control signal, wherein the first driving unit turns on the first level control unit in response to a front edge of an input signal and turns off the first level control unit when the level of the first control signal of the next stage is higher than the level of a second control signal that is input to the first level control unit;   a second level control unit for providing a first voltage to the output terminal;   a second driving unit for turning off the second level control unit in response to the front edge of the first control signal and turning on the second level control unit in response to the rear edge of the first control signal; and   a third level control unit for providing the first voltage to the output terminal when the level of the first control signal of the next stage is higher than the level of the second control signal that is input to the third level control unit, wherein:   when both the signal at the output terminal and the first control signal are at high levels, the second control signal is also at a high level.   
     
     
         2 . The shift register according to  claim 1 , wherein the third level control unit comprises:
 a first transistor, wherein the gate receives the first control signal of the next stage, the first source/drain is coupled to the output terminal, and the second source/drain receives the second control signal that is equal to the first clock signal.   
     
     
         3 . The shift register according to  claim 2 , wherein the first driving unit comprises:
 a third transistor, wherein the gate receives the first control signal of the next stage, the first source/drain is coupled to the first node, and the second source/drain receives the second control signal.   
     
     
         4 . The shift register according to  claim 3 , wherein the first driving unit further comprises:
 a fifth transistor, wherein the gate receives the input signal, the first source/drain receives a second voltage, and the second source/drain is coupled to the first node.   
     
     
         5 . The shift register according to  claim 3 , wherein the first driving unit further comprises:
 a fourth transistor, wherein the gate is coupled to the second driving unit via a second node for receiving a third control signal, the first source/drain is coupled to the first node, and the second source/drain receives the first voltage.   
     
     
         6 . The shift register according to  claim 3 , wherein the first driving unit further comprises:
 a fifth transistor, wherein the gate receives a second clock signal, the first source/drain is coupled to the first node, the second source/drain receives the input signal, the fifth transistor provides the input signal to the first node when the level of the second clock signal is higher than the input signal;   wherein the enabling time of the second clock signal and the enabling time of the first clock signal are non-overlapped, and the second clock signal is delayed by a two quarter period with respect to the first clock signal.   
     
     
         7 . The shift register according to  claim 1 , wherein the second driving unit comprises:
 a bias voltage unit coupled to the input terminal of the second level control unit via the second node for providing the third control signal, wherein the bias voltage unit pulls down the level of the third control signal to turn off the second level control unit in response to the front edge of the first control signal and pulls up the level of the third control signal to turn on the second level control unit in response to the rear edge of the first control signal.   
     
     
         8 . The shift register according to  claim 7 , wherein the second driving unit further comprises:
 a sixth transistor, wherein the gate receives a second clock signal, the first source/drain receives a second voltage, and the second source/drain is coupled to the second node.   
     
     
         9 . The shift register according to  claim 7 , wherein the second level control unit comprises:
 a ninth transistor, wherein the gate receives the third control signal, the first source/drain is coupled to the output terminal, and the second source/drain receives the first voltage.   
     
     
         10 . The shift register according to  claim 9 , wherein further comprises:
 a fourth level control unit comprising a second transistor, wherein the gate receives a second clock signal, the first source/drain is coupled to the output terminal, the second source/drain receives the first voltage, the second transistor provides the first voltage to the output terminal in response to a rising edge of the second clock signal;   wherein the enabling time of the second clock signal and of the first clock signal the enabling time are non-overlapped.   
     
     
         11 . The shift register according to  claim 1 , wherein the first level control unit comprises:
 a seventh transistor, wherein the gate receives the first control signal, the first source/drain receives the first clock signal, and the second source/drain is coupled to the output terminal.   
     
     
         12 . The shift register according to  claim 1 , wherein a first stage among the stages receives an initial signal used as the input signal. 
     
     
         13 . The shift register according to  claim 1 , wherein the enabling times of the first clock signals received by any two adjacent stages are non-overlapped, and a first clock signal received by next stage is delayed by a two quarter period with respect to the first clock signal.