Method of handling reference cells in nvm arrays

Abstract

A memory chip includes memory cells storing data to be read; at least one reference cell having a reference cell current level and a reference gate voltage adjuster to adjust, for each reference cell, a reference gate voltage level to compensate for a shift of the reference cell current level from an original current level.

1 . A memory chip comprising:
 memory cells storing data to be read;   at least one reference cell having a reference cell current level; and   a reference gate voltage adjuster to adjust, for each said reference cell, a reference gate voltage level to compensate for a shift of said reference cell current level from an original current level.   
     
     
         2 . The memory chip according to  claim 1  and wherein said reference gate voltage adjuster comprises a unit to change said reference gate voltage level from said an original reference gate voltage level in steps and to stop changing said reference gate voltage level when a predefined margin is achieved. 
     
     
         3 . The memory chip according to  claim 2  and wherein said unit operates on a representative distribution. 
     
     
         4 . The memory chip according to  claim 3  and wherein said unit determines a difference between said original reference gate voltage level and a resultant reference gate voltage level and wherein said adjuster adds said difference to a fixed gate voltage used by said chip for reading. 
     
     
         5 . The memory chip according to  claim 2  and wherein said margin is defined with respect to an associated distribution. 
     
     
         6 . A method for a memory chip, the method comprising:
 for each reference cell of said memory array, adjusting a reference gate voltage level to compensate for a shift of a reference cell current level from an original current level.   
     
     
         7 . The method according to  claim 6  and wherein said adjusting comprises changing said reference gate voltage level from said fixed gate voltage level in steps and stopping to change said reference gate voltage level when a predefined margin is achieved. 
     
     
         8 . The method according to  claim 7  and wherein said changing comprises determining a difference between said original reference gate voltage level and a resultant reference gate voltage level and wherein said adjusting comprises adding said difference to a fixed gate voltage used by said chip for reading. 
     
     
         9 . The method according to  claim 8  and wherein said determining uses a representative distribution as a reference to detect change in reference cell current. 
     
     
         10 . The method according to  claim 6  and wherein said memory cells are multi-level cells. 
     
     
         11 . The method according to  claim 6  and wherein said memory cells are single level cells.