Integrated circuit with compress engine

Abstract

An integrated circuit and method for modifying data by compressing the data in third dimensional memory technology is disclosed. In a specific embodiment, an integrated circuit is configured to perform compression of data disposed in third dimensional memory. For example, the integrated circuit can include a third dimensional memory array configured to store an input independent of storing a compressed copy of the input, a processor configured to compress the input to form the compressed copy of the input, and a controller configured to control access between the processor and the third dimensional memory array. The third dimension memory array can include one or more layers of non-volatile re-writeable two-terminal cross-point memory arrays fabricated back-end-of-the-line (BEOL) over a logic layer fabricated front-end-of-the-line (FEOL). The logic layer includes active circuitry for data operations (e.g., read and write operations) and data compression operations on the third dimension memory array.

1 . An integrated circuit (IC), comprising:
 a die including a front-end-of-the-line (FEOL) portion having active circuitry fabricated on a semiconductor substrate and a back-end-of-the-line (BEOL) portion in contact with and vertically fabricated directly above the FEOL portion, the BEOL and FEOL portions comprise a unitary whole;   a memory layer including embedded therein a re-writeable non-volatile two-terminal cross-point memory array configured to store an input independent of storing a compressed copy of the input, the memory layer included in the BEOL portion;   a processor included in the active circuitry and configured to compress the input to form the compressed copy of the input; and   a controller included in the active circuitry and configured to control access between the processor and the re-writeable non-volatile two-terminal cross-point memory array.   
     
     
         2 . The IC of  claim 1 , wherein the active circuitry includes a port circuit configured to provide a plurality of access ports to the re-writeable non-volatile two-terminal cross-point memory array. 
     
     
         3 . The IC of  claim 1 , wherein the active circuitry includes a priority circuit configured to resolve a request from more than one of the plurality of access ports to the re-writeable non-volatile two-terminal cross-point memory array. 
     
     
         4 . The IC of  claim 1  and further comprising:
 a processor memory included in a portion of the re-writeable non-volatile two-terminal cross-point memory array, the portion of the re-writeable non-volatile two-terminal cross-point memory array being configured to store data used by the processor. 
 
     
     
         5 . The IC of  claim 1 , wherein the controller includes of a scatter-gather circuit, the scatter-gather circuit being configured to locate the input across multiple memory layers in the re-writeable non-volatile two-terminal cross-point memory array. 
     
     
         6 . The IC of  claim 5 , wherein the scatter-gather circuit is configured to locate the compressed copy of the input across the multiple memory layers. 
     
     
         7 . An integrated circuit (IC), comprising:
 a die including a front-end-of-the-line (FEOL) portion having active circuitry fabricated on a semiconductor substrate and a back-end-of-the-line (BEOL) portion in contact with and vertically fabricated directly above the FEOL portion, the BEOL and FEOL portions comprise a unitary whole;   a re-writeable non-volatile two-terminal cross-point memory array included in a memory layer of the BEOL portion, wherein the re-writeable non-volatile two-terminal cross-point memory array is configured to store an input independent of storing a compressed copy of the input;   a processor included in the active circuitry and configured to transform the input to form a compressed data;   a controller included in the active circuitry and configured to control a request from the processor to access the re-writeable non-volatile two-terminal cross-point memory array;   a port circuit included in the active circuitry and configured to provide a plurality of access ports to the re-writeable non-volatile two-terminal cross-point memory array;   a priority circuit included in the active circuitry and configured to resolve multiple requests from the port circuit to access the re-writeable non-volatile two-terminal cross-point memory array; and   a processor memory included in a portion of the re-writeable non-volatile two-terminal cross-point memory array, the portion of the re-writeable non-volatile two-terminal cross-point memory array being configured to store data used by the processor.   
     
     
         8 . The IC of  claim 7 , wherein the controller uses a scatter-gather circuit included in the active circuitry and configured to locate a first input on a common memory layer in the re-writeable non-volatile two-terminal cross-point memory array with a second input to form the compressed data. 
     
     
         9 . The IC of  claim 7 , wherein the controller uses a scatter-gather circuit included in the active circuitry and configured to locate a first input on a different memory layer in the re-writeable non-volatile two-terminal cross-point memory array from a second input to form the compressed data. 
     
     
         10 . The IC of  claim 7 , wherein the controller replaces the input with the compressed copy of the input. 
     
     
         11 . The IC of  claim 7 , wherein the controller is operative to request the storing of the compressed copy of the input on a separate memory layer in the re-writeable non-volatile two-terminal cross-point memory array from the input. 
     
     
         12 . The IC of  claim 7 , wherein the controller is operative to request the storing of the compressed copy of the input on a common memory layer in the re-writeable non-volatile two-terminal cross-point memory array to the input. 
     
     
         13 . The IC of  claim 7 , wherein the controller maps a portion of the input discontinued from another portion of the input across more than one memory layer in the re-writeable non-volatile two-terminal cross-point memory array using a scatter-gather circuit that is included in the active circuitry. 
     
     
         14 . The IC of  claim 7 , wherein the controller uses the t re-writeable non-volatile two-terminal cross-point memory array to store the compressed copy of the input in parallel to sending the input from storage to the processor. 
     
     
         15 . The IC of  claim 7 , wherein the processor is configured to compress the input prior to completing storage of the input in the re-writeable non-volatile two-terminal cross-point memory array. 
     
     
         16 . The IC of  claim 7  and further comprising: an analog-to-digital converter (ADC) configured to receive an input data and to generate an output data that is uncompressed and stored directly in the re-writeable non-volatile two-terminal cross-point memory array without using a frame buffer to temporarily store the output data. 
     
     
         17 . The IC of  claim 16 , wherein the uncompressed output data from the ADC is compressed during or after reception of the input data, and the output data is compressed in an operation that is independent of the storing of the input or the storing of the compressed copy of the input. 
     
     
         18 . The IC of  claim 7 , wherein the processor is configured to uncompress the compressed data. 
     
     
         19 . The IC of  claim 7  and further comprising: direct memory access (DMA) circuitry included in the active circuitry and operative to perform multiple DMA transfers of data to and from the re-writeable non-volatile two-terminal cross-point memory array. 
     
     
         20 . The IC of  claim 7 , wherein the memory layer includes memory allocated for one or more types of data selected from the group consisting of scatter-gather memory, processor memory, data memory, processor mailbox, pointer table, stored input, unused memory, stored compressed input, port pointer, command, address pointer, transfer count pointer, chain marker, and end marker.