Storing context information prior to not supplying power to a processor

Abstract

A CPU ( 1 ) automatically preserves the CPU context in a computer memory ( 5 ) that remains powered-up when the CPU is powered down in sleep mode. By means of the preserved CPU context, the CPU is able to instantly and transparently resume program execution at the instruction of the program that was asserted for execution when the CPU was powered down. The CPU is permitted to power down frequently, even during execution of a program, and results in reduced average overall power consumption.

1 - 14 . (canceled) 
     
     
         15 . A computing system, comprising:
 a processing device;   a first memory configured to have data stored in the first memory accessible by the processing device and configured to not have the data stored in the first memory accessible by other devices included in the computing system; and   a second memory configured to be accessible to the processing device and the other devices included in the computing system;   wherein the computing system is configured to allow power to be supplied to the first memory during a time at which power is not supplied to the processing device and the second memory and wherein in response to the processing device detecting a command to inactivate a clock signal supplied to the processing device, the processing device is operable to store context information in the first memory and the computing system is configured to not supply the power to the processing device after the context information is stored in the first memory and not supply the power to the second memory.   
     
     
         16 . The computing system of  claim 15 , configured to restore the context information from the first memory in response to the computing system resupplying the power to the processing device. 
     
     
         17 . The computing system of  claim 16 , wherein the context information is restored from the first memory to the processing device's internal memory. 
     
     
         18 . The computing system of  claim 17 , wherein the processing device's internal memory and the processing device are in different power domains. 
     
     
         19 . The computing system of  claim 15 , wherein the first memory and the processing device are in different power domains. 
     
     
         20 . The computing system of  claim 15 , configured to set a flag in response to not supplying the power to the processing device to indicate the context information is stored in the first memory, wherein the flag is checked in response to the computing system resupplying the power to the processing device. 
     
     
         21 . The computing system of  claim 15 , wherein the command is in response to detecting a prescribed period of inactivity. 
     
     
         22 . The computing system of  claim 15 , configured to monitor a user input device for activity and to resupply the power to the processing device in response to detecting the activity. 
     
     
         23 . The computing system of  claim 15 , operable for executing a program comprising a first instruction and a next instruction in an instruction set; wherein operations performed by the processing device and the computing system after detecting the command are performed after the first instruction is executed and before the next instruction is executed, wherein the next instruction is executed after the power is resupplied to the processing device. 
     
     
         24 . A method, comprising:
 supplying power to a processing device included in a computing system;   supplying power to a first memory, wherein the first memory is configured to have data stored in the first memory accessible by the processing device and configured to not have the data stored in the first memory accessible by other devices included in the computing system;   supplying power to a second memory, wherein the second memory is configured to be accessible to the processing device and the other devices included in the computing system;   detecting a command to inactivate a clock signal supplied to the processing device;   in response to the detecting the command, storing context information in the first memory using the processing device;   stopping the supplying of the power to the processing device using the computing system in response to completion of the storing the context information in the first memory; and   stopping the supplying of the power to the second memory.   
     
     
         25 . The method of  claim 24 , further comprising restoring the context information from the first memory in response to the computing system resupplying the power to the processing device. 
     
     
         26 . The method of  claim 25 , wherein the context information is restored from the first memory to the processing device's internal memory. 
     
     
         27 . The method of  claim 26 , wherein the processing device's internal memory and the processing device are in different power domains. 
     
     
         28 . The method of  claim 24 , wherein the first memory and the processing device are in different power domains. 
     
     
         29 . The method of  claim 24 , further comprising:
 setting a flag in response to not supplying the power to the processing device to indicate the context information is stored in the first memory; and   checking the flag in response to the computing system resupplying the power to the processing device.   
     
     
         30 . The method of  claim 24 , wherein the command is in response to detecting a prescribed period of inactivity. 
     
     
         31 . The method of  claim 24 , further comprising:
 monitoring a user input device for activity; and   resupplying the power to the processing device in response to detecting the activity.   
     
     
         32 . The method of  claim 24 , further comprising:
 executing a program comprising a first instruction and a next instruction in an instruction set;   after executing the first instruction and before executing the next instruction, detecting the command, storing the context information, and stopping the supplying of the power to the processing device and to the second memory;   restoring the context information from the first memory in response to resupplying the power to the processing device and before executing the next instruction; and   executing the next instruction after the power is resupplied to the processing device.