Flash Memory Device

Abstract

A flash memory device including a semiconductor substrate that includes selection transistor regions and a memory cell region defined between the selection transistor region, first isolation layers formed in the selection transistor regions, and second isolation layers formed in the memory cell region. The second isolation layers have a lower height than the first isolation layers.

1 . A flash memory device, comprising:
 a semiconductor substrate comprising selection transistor regions and a memory cell region defined between the selection transistor regions;   first isolation layers formed in the selection transistor regions; and   second isolation layers formed in the memory cell region, wherein the second isolation layers have a lower height than the first isolation layers.   
     
     
         2 . The flash memory device of  claim 1 , wherein the semiconductor substrate further comprises:
 a peripheral region, and   third isolation layers formed in the peripheral region and having a same height as the first isolation layers.   
     
     
         3 . The flash memory device of  claim 1 , further comprising:
 a gate insulating layer and conductive layers stacked over the semiconductor substrate between adjacent first isolation layers; and   select lines configured to come in contact with the conductive layers and the first isolation layers.   
     
     
         4 . The flash memory device of  claim 3 , wherein the first isolation layers and the second isolation layers have a higher height than the gate insulating layer. 
     
     
         5 . The flash memory device of  claim 3 , wherein a top surface of each of the conductive layers are recessed and concave. 
     
     
         6 . The flash memory device of  claim 3 , wherein the first isolation layers have a lower height than the conductive layers, and the select lines are in contact with a top surface and sidewalls of the first conductive layers. 
     
     
         7 . The flash memory device of  claim 1 , wherein:
 the selection transistor regions comprise a source selection transistor region and a drain selection transistor region, and   the memory cell region is defined between the source selection transistor region and the drain selection transistor region.   
     
     
         8 . The flash memory device of  claim 1 , wherein the first isolation layers and the second isolation layers are adjacent and coupled to each other. 
     
     
         9 . The flash memory device of  claim 3 , wherein the first isolation layer has a same height as the conductive layer. 
     
     
         10 . The flash memory device of  claim 9 , wherein a top surface of each of the conductive layers is recessed and concave.