Digital Potentiometer Using Third Dimensional Memory

Abstract

A digital potentiometer using third dimensional memory includes a switch configured to electrically couple one or more resistive elements with a first pin and a second pin, and a non-volatile register configured to control the switch. In one example, the non-volatile register can include a BEOL non-volatile memory element, such as a third dimensional memory element. The non-volatile register can include a FEOL active circuitry portion that is electrically coupled with the BEOL non-volatile memory element to implement the non-volatile register. The resistive elements can be BEOL resistive elements that can be fabricated on the same plane or a different plane than the BEOL non-volatile memory elements. The BEOL non-volatile memory elements and the BEOL resistive elements can retain stored data in the absence of power and the stored data can be non-destructively determined by application of a read voltage.

1 . A variable resistance device, comprising:
 an integrated circuit die including a front-end-of-the-line (FEOL) portion comprised of active circuitry fabricated FEOL on a semiconductor substrate and a back-end-of-the-line (BEOL) portion including a vertically stacked layer of memory, the BEOL portion is in contact with and is vertically fabricated BEOL directly above the FEOL portion;   a plurality of resistive elements included in the vertically stacked layer of memory, each resistive element having exactly two terminals;   
       non-volatile memory cells included in the vertically stacked layer of memory and configured to select a subset of the plurality of resistive elements, each non-volatile memory cell having exactly two terminals; and
 a configuration circuit included in the active circuitry and configured to configure a subset of the non-volatile memory cells. 
 
     
     
         2 . The variable resistance device of  claim 1 , wherein the non-volatile memory cells are configured to select a subset of the plurality of resistive elements substantially at power-up. 
     
     
         3 . The variable resistance device of  claim 1 , wherein at least one of the plurality of resistive elements has an adjustable resistance that is adjusted by applying a voltage across its two terminals, the voltage operative to change a resistive state of at least one of the plurality of resistive elements. 
     
     
         4 . The variable resistance device of  claim 1 , wherein at least one of the plurality of resistive elements comprises a resistive memory element (RME) having exactly two terminals, the RME having an adjustable resistance that varies as a function of a voltage differential applied across the two terminals of the RME. 
     
     
         5 . The variable resistance device of  claim 4 , wherein each RME includes a tunnel barrier layer and a conductive oxide layer that are electrically in series with each other and with the two terminals of the RME. 
     
     
         6 . The variable resistance device of  claim 4 , wherein each RME includes a tunnel barrier and an ion reservoir that are electrically in series with each other and with the two terminals of the RME. 
     
     
         7 . The variable resistance device of  claim 6 , wherein the ion reservoir includes mobile oxygen ions. 
     
     
         8 . The variable resistance device of  claim 4 , wherein each RME is positioned in a two-terminal cross-point array. 
     
     
         9 . The variable resistance device of  claim 1 , wherein each resistive element includes a tunnel barrier layer and a conductive oxide layer that are electrically in series with each other and with the two terminals of the resistive element. 
     
     
         10 . The variable resistance device of  claim 1 , wherein each non-volatile memory cell includes a tunnel barrier layer and a conductive oxide layer that are electrically in series with each other and with the two terminals of the non-volatile memory cell. 
     
     
         11 . The variable resistance device of  claim 1 , wherein the plurality of resistive elements are positioned in a two-terminal cross-point array. 
     
     
         12 . The variable resistance device of  claim 1 , wherein the non-volatile memory cells are positioned in a two-terminal cross-point array. 
     
     
         13 . The variable resistance device of  claim 1  and further comprising: a plurality of vertically stacked layers of memory in the BEOL portion. 
     
     
         14 . The variable resistance device of  claim 1  and further comprising:
 a first pin positioned in the FEOL portion and electrically coupled with at least one of the plurality of resistive elements; 
 a second pin positioned in the FEOL portion; 
 a routing circuit included in the active circuitry and electrically coupled with the second pin; and 
 a plurality of non-volatile registers, each non-volatile register including register logic (RL) in the active circuitry and a non-volatile memory element in the vertically stacked layer of memory, the plurality of non-volatile registers are electrically coupled with the configuration circuit and the routing circuit, 
 wherein the plurality of non-volatile registers and the routing circuit are configured to generate a variable electrical resistance between the first pin and second pin in response to control signals from the configuration circuit. 
 
     
     
         15 . The variable resistance device of  claim 1 , wherein each resistive element includes a tunnel barrier and an ion reservoir that are electrically in series with each other and with the two terminals of the resistive element. 
     
     
         16 . The variable resistance device of  claim 15 , wherein the ion reservoir includes mobile oxygen ions. 
     
     
         17 . The variable resistance device of  claim 1 , wherein each non-volatile memory cell includes a tunnel barrier and an ion reservoir that are electrically in series with each other and with the two terminals of the non-volatile memory cell. 
     
     
         18 . The variable resistance device of  claim 17 , wherein the ion reservoir includes mobile oxygen ions. 
     
     
         19 . The variable resistance device of  claim 1 , wherein each non-volatile memory cell consists essentially of a memory element (ME) having exactly two terminals and the ME is electrically in series with the two terminals of its respective non-volatile memory cell. 
     
     
         20 . The variable resistance device of  claim 1 , wherein each resistive element consists essentially of a memory element (ME) having exactly two terminals and the ME is electrically in series with the two terminals of its respective resistive element.