Semiconductor device and method of manufacturing the same, and power supply apparatus

Abstract

A semiconductor device includes an electrode material diffusion suppression layer provided either between a gate electrode and a gate insulation film, between Al-containing ohmic electrodes and an Au interconnection, and below the gate electrode and above the Al-containing ohmic electrodes, the electrode material diffusion suppression layer having a structure wherein a first the TaN layer, a Ta layer, and a second the TaN layer are stacked in sequence.

1 . A semiconductor device comprising:
 a gate electrode;   a gate insulation film; and   an electrode material diffusion suppression layer, provided between the gate electrode and the gate insulation film, comprising a first TaN layer, a Ta layer, and a second TaN layer stacked in sequence.   
     
     
         2 . The semiconductor device according to  claim 1 , wherein the gate electrode comprises at least one layer including any material selected from Pt, Ir, W, Ni, Ti, Au, Cu, Ag, Pd, Zn, Cr, Al, Mn, Ta, Si, TaN, TiN, Ru, CoSi, WSi, NiSi, MoSi, TiSi, AlSi, AlCu, and AlSiCu. 
     
     
         3 . The semiconductor device according to  claim 1 , wherein the gate insulation film comprises at least one layer including any material selected from AlO, SiN, SiO, HfO, and AlN. 
     
     
         4 . The semiconductor device according to  claim 1 , further comprising a layer, provided at least one of between the gate electrode and the electrode material diffusion suppression layer, and between the gate insulation film and the electrode material diffusion suppression layer, comprising at least one layer including any material selected from Pt, Ir, W, Ni, Ti, Au, Cu, Ag, Pd, Zn, Cr, Al, Mn, Ta, Si, TaN, TiN, Ru, CoSi, WSi, NiSi, MoSi, TiSi, AlSi, AlCu, and AlSiCu. 
     
     
         5 . The semiconductor device according to  claim 1 , further comprising a nitride semiconductor stacked structure comprising a carrier transit layer and a carrier supply layer,
 wherein the gate insulation film is provided over the nitride semiconductor stacked structure.   
     
     
         6 . A semiconductor device comprising:
 an ohmic electrode comprising an Al layer;   an Au interconnection; and   an electrode material diffusion suppression layer, provided between the Al layer and the Au interconnection, comprising a first TaN layer, a Ta layer, and a second TaN layer stacked in sequence.   
     
     
         7 . The semiconductor device according to  claim 6 , further comprising a layer, provided at least one of between the Au interconnection and the electrode material diffusion suppression layer and between the Al layer, and the electrode material diffusion suppression layer, comprising at least one layer including any material selected from Pt, Ir, W, Ni, Ti, Au, Cu, Ag, Pd, Zn, Cr, Al, Mn, Ta, Si, TaN, TiN, Ru, CoSi, WSi, NiSi, MoSi, TiSi, AlSi, AlCu, and AlSiCu. 
     
     
         8 . The semiconductor device according to  claim 1 , wherein the electrode material diffusion suppression layer further comprises a Pt layer stacked on the second TaN layer. 
     
     
         9 . The semiconductor device according to  claim 1 , wherein the electrode material diffusion suppression layer further comprises an Ag layer stacked on the second TaN layer. 
     
     
         10 . The semiconductor device according to  claim 1 , wherein the electrode material diffusion suppression layer further comprises a Ti layer stacked on the second TaN layer. 
     
     
         11 . The semiconductor device according to  claim 1 , wherein the electrode material diffusion suppression layer further comprises a Cu layer stacked on the second TaN layer. 
     
     
         12 . The semiconductor device according to  claim 1 , wherein the first and second TaN layers have nitrogen contents of greater than 48% but not greater than 52%. 
     
     
         13 . A semiconductor device comprising:
 a first electrode material diffusion suppression layer, provided under a gate electrode, comprising a TaN layer, a Ta layer, and a TaN layer stacked in sequence; and   a second electrode material diffusion suppression layer, provided over an ohmic electrode, comprising a TaN layer, a Ta layer, and a TaN layer stacked in sequence.   
     
     
         14 . A power supply apparatus comprising:
 a semiconductor device comprising:
 a gate electrode; 
 a gate insulation film; and 
 an electrode material diffusion suppression layer, provided between the gate electrode and the gate insulation film, comprising a first TaN layer, a Ta layer, and a second TaN layer stacked in sequence. 
   
     
     
         15 . A power supply apparatus comprising:
 a semiconductor device comprising:
 an ohmic electrode comprising an Al layer; 
 an Au interconnection; and 
 an electrode material diffusion suppression layer, provided between the Al layer and the Au interconnection, comprising a first TaN layer, a Ta layer, and a second TaN layer stacked in sequence. 
   
     
     
         16 . A power supply apparatus comprising:
 a semiconductor device comprising:
 a first electrode material diffusion suppression layer, provided under a gate electrode, comprising a TaN layer, a Ta layer, and a TaN layer stacked in sequence; and 
 a second electrode material diffusion suppression layer, provided over an ohmic electrode, comprising a TaN layer, a Ta layer, and a TaN layer stacked in sequence. 
   
     
     
         17 . A method of manufacturing a semiconductor device, comprising:
 forming a gate insulation film;   forming an electrode material diffusion suppression layer by stacking a first TaN layer, a Ta layer, and a second TaN layer, in sequence, over the gate insulation film; and   forming a gate electrode over the electrode material diffusion suppression layer.   
     
     
         18 . A method of manufacturing a semiconductor device, comprising:
 forming an ohmic electrode comprising an Al layer;   forming an electrode material diffusion suppression layer by stacking a first TaN layer, a Ta layer, and a second TaN layer, in sequence, over the Al layer; and   forming an Au interconnection over the electrode material diffusion suppression layer.   
     
     
         19 . A method of manufacturing a semiconductor device, comprising:
 forming a first electrode material diffusion suppression layer by stacking a TaN layer, a Ta layer, and a TaN layer, in sequence;   forming a gate electrode over the first electrode material diffusion suppression layer;   forming an ohmic electrode; and   forming a second electrode material diffusion suppression layer by stacking a TaN layer, a Ta layer, and a TaN layer, in sequence, over the ohmic electrode.   
     
     
         20 . The method of manufacturing a semiconductor device according to  claim 19 , wherein the first electrode material diffusion suppression layer and the second electrode material diffusion suppression layer are formed simultaneously.