US2012217942A1PendingUtilityA1

Semiconductor circuit and switching power supply apparatus

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Assignee: KUDO RYOTAROPriority: Aug 8, 2007Filed: May 7, 2012Published: Aug 30, 2012
Est. expiryAug 8, 2027(~1.1 yrs left)· nominal 20-yr term from priority
Inventors:Ryotaro Kudo
H10W 90/756H10W 90/753H10W 72/07554H10W 72/07552H10W 72/5475H10W 72/5473H10W 72/932H10W 72/926H10W 72/552H10W 72/547H10W 72/527H02M 3/1584H02M 1/007
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Claims

Abstract

The power supply apparatus realizes a high-speed response, a stable operation, and a low output ripple with low power consumption. The first stage switching regulator receives an input voltage and forms a first voltage. The second stage switching regulator receives the first voltage and forms a second voltage. The second stage switching regulator includes an N-phase (N is two or more) switching regulator, and the first voltage is set to be N times a target value of the second voltage. The input voltage is set to be higher than the first voltage.

Claims

exact text as granted — not AI-modified
1 . A method comprising:
 providing a code for designating an operation voltage of a system control unit;   providing a first control signal and a second control signal according to the code provided from the system control unit;   providing a first voltage lower than an input voltage from a first switching regulator which receives the input voltage and the first control signal, the first voltage being set according to the first control signal; and   providing a second voltage lower than the first voltage to the system control unit as the operation voltage thereof from a second switching regulator, the second voltage being set according to the second control signal,   
     
     
         2 . A method according to  claim 1 ,
 wherein the second switching regulator includes an N-phase (N is two or more) switching regulator that has N output circuits.   
     
     
         3 . A method according to  claim 2 ,
 wherein the first switching regulator is a single-phase switching regulator operated by a first PWM pulse.   
     
     
         4 . A method according to  claim 1 ,
 wherein the system control unit is a CPU.

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