Test circuit, semiconductor memory apparatus using the same, and test method of the semiconductor memory apparatus

Abstract

A test circuit of a semiconductor memory apparatus includes: a test control signal generating unit configured to enable a control signal if an active signal is enabled after a test signal is enabled, and substantially maintain the control signal in an enable state until a precharge timing signal is enabled; and a precharge control unit configured to invert the control signal to output the inverted signal as a bit line precharge signal when a preliminary bit line precharge signal is in a disable state.

1 . A test method of a semiconductor memory apparatus comprising: storing data of a specific voltage level in a plurality of mats of a semiconductor memory apparatus having an open bit line structure and enabling the plurality of mats; precharging either one of an even-numbered or odd-numbered sense amplifier group and substantially maintaining a precharge state; and enabling another sense amplifier group which is not precharged and outputting the data. 
     
     
         2 . The test method of  claim 1 , further comprising releasing the sense amplifier group that is precharged from a precharging state after a predetermined time elapses. 
     
     
         3 . The test method of  claim 2 , further comprising: storing data of the specific voltage level in the plurality of mats and enabling the plurality of mats; precharging the another sense amplifier group which is not precharged and substantially maintaining the precharging state; and enabling the another sense amplifier group which is not precharged and outputting the stored data.