Efficient buffering for a system having non-volatile memory

Abstract

Systems and methods are disclosed for efficient buffering for a system having non-volatile memory (“NVM”). In some embodiments, a control circuitry of a system can use heuristics to determine whether to perform buffering of one or more write commands received from a file system. In other embodiments, the control circuitry can minimize read energy and buffering overhead by efficiently re-ordering write commands in a queue along page-aligned boundaries of a buffer. In further embodiments, the control circuitry can optimally combine write commands from a buffer with write commands from a queue. After combining the commands, the control circuitry can dispatch the commands in a single transaction.

1 . A method for splitting data writes into multiple write paths, the method comprising:
 receiving a first write command from a file system for programming to a non-volatile memory (“NVM”);   saving the first write command in a queue;   determining the size of the first write command;   determining whether to perform buffering based at least in part on the size of the first write command; and   in response to determining to perform buffering, transferring the first write command from the queue to a buffer.   
     
     
         2 . The method of  claim 1 , wherein in response to determining not to perform buffering, dispatching the first write command from the queue to the NVM. 
     
     
         3 . The method of  claim 2 , further comprising:
 determining whether the amount of time that has elapsed since a last dispatched write command is less than a pre-determined time period; and   in response to determining that the amount of time that has elapsed since a last dispatched write command is less than the pre-determined time period, waiting to receive additional write commands in the queue before dispatching the first write command from the queue to the NVM.   
     
     
         4 . The method of  claim 1 , wherein the determining whether to perform buffering further comprises:
 determining if the size of the first write command is below a pre-determined threshold; and   in response to determining that the size of the first write command is below the pre-determined threshold, determining whether the number of write commands saved in the queue exceeds a pre-determined number.   
     
     
         5 . The method of  claim 4 , further comprises:
 in response to determining that the number of write commands saved in the queue exceeds the pre-determined number, combining the write commands into a write-multi command; and   dispatching the write-multi command from the queue to the NVM.   
     
     
         6 . The method of  claim 1 , wherein the determining whether to perform buffering further comprises:
 determining whether a set of most recently receive write commands in the queue is sequential;   in response to determining that the set of the most recently receive write commands is sequential, waiting to receive additional write commands in the queue.   
     
     
         7 . The method of  claim 6 , further comprising:
 receiving at least one additional write command from the file system;   combining the at least one additional write command with the set of most recently received write commands into a write-multi command; and   dispatching the write-multi command from the queue to the NVM.   
     
     
         8 . A memory interface for accessing a non-volatile memory (“NVM”), the memory interface comprising:
 a bus controller operative to communicate with the NVM; and 
 control circuitry operative to:
 receive a first write command in a queue; 
 apply at least one heuristic to the first write command in order to determine whether to transfer the first write command to a buffer; 
 in response to determining not to transfer the first write command to the buffer, direct an encryption module to encrypt the first write command; and 
 direct the bus controller to dispatch the encrypted write command to the NVM. 
 
 
     
     
         9 . The memory interface of  claim 8 , wherein the control circuitry is further operative to direct the bus controller to dispatch the encrypted write command to a direct memory access (“DMA”) engine. 
     
     
         10 . The memory interface of  claim 8 , wherein in response to determining to transfer the first write command to the buffer, the control circuitry is further operative to:
 direct the encryption module to encrypt the first write command; and   store the encrypted write command in the buffer.   
     
     
         11 . The memory interface of  claim 8 , wherein in response to determining to transfer the first write command to the buffer, the control circuitry is further operative to:
 copy at least one encryption seed to the volatile memory; and   store the first write command in the buffer.   
     
     
         12 . The memory interface of  claim 8 , wherein the at least one heuristic comprises at least one of the size of the first write command, the number of dispatched write commands immediately preceding the first write command, the number of remaining write commands saved in the queue, the amount of available space in the volatile memory, a size of the buffer, and input/output patterns. 
     
     
         13 . The memory interface of  claim 12 , wherein the control circuitry is further operative to:
 determine if the size of the first write command is the same as or larger than the size of the buffer;   in response to determining that the size of the first write command is the same as or larger than the size of the buffer, determine not to transfer the first write command to the buffer.   
     
     
         14 . The memory interface of  claim 12 , wherein the control circuitry is further operative to:
 determine if the number of dispatched write commands immediately preceding the first write command exceeds a pre-determined number;   in response to determining that the number of write commands exceeds the pre-determined number, wait to receive at least one additional write command in the queue.   
     
     
         15 . The memory interface of  claim 14 , wherein the control circuitry is further operative to:
 receive at least one additional write command in the queue;   combine the at least one additional write command with the first write command into a write-multi command; and   direct the bus controller to dispatch the write-multi command from the queue to the NVM.   
     
     
         16 . The memory interface of  claim 8 , wherein the control circuitry is further operative to:
 receive at least one side-band signal; and   direct the bus controller to dispatch all of the commands stored in the buffer to the NVM.   
     
     
         17 . A method for combining write commands for dispatch to a non-volatile memory (“NVM”), the method comprising:
 selecting at least a first write command from a queue and at least a second write command from a buffer, wherein the at least the first and second write commands are selected to minimize page crossings in the NVM; 
 combining the at least the first and second write commands to form a write-multi command; and 
 dispatching the write-multi command to the NVM. 
 
     
     
         18 . The method of  claim 17 , wherein the combining the at least the first and second write commands further comprises applying at least a first encryption seed to the at least the first write command. 
     
     
         19 . The method of  claim 18 , wherein the at least the second write command is unencrypted. 
     
     
         20 . The method of  claim 19 , wherein the combining the at least the first and second write commands further comprises:
 retrieving at least a second encryption seed from volatile memory; and   applying the at least the second encryption seed to the at least the second write command.   
     
     
         21 . A system comprising:
 a non-volatile memory (“NVM”) comprising a plurality of pages;   a bus controller operative to communicate with the NVM;   volatile memory comprising a queue and a buffer for storing a set of write commands; and   control circuitry operative to:
 determine if the set of write commands stored in the buffer is currently aligned with at least one page boundary; 
 in response to determining that the set of write commands stored in the buffer is not currently aligned with the at least one page boundary, detect a fill size that is needed to fill the buffer to the at least one page boundary; 
 determine if there is at least one write command in the queue that has a size equal to the fill size; and 
 in response to determining that there is at least one write command in the queue that has a size equal to the fill size, transfer the at least one write command from the queue to the buffer. 
   
     
     
         22 . The system of  claim 21 , wherein the control circuitry is operative to use a best-fit algorithm to determine if there is at least one write command in the queue that has a size equal to the fill size. 
     
     
         23 . The system of  claim 21 , wherein in response to determining that the set of write commands stored in the buffer is currently aligned with the at least one page boundary, the control circuitry is operative to:
 combine the set of write commands into a write-multi command; and   direct the bus controller to dispatch the write-multi command from the buffer to the NVM.   
     
     
         24 . The system of  claim 21 , wherein the control circuitry is operative to:
 receive at least one side-band signal;   fill the buffer to the end of at least one page-aligned portion with invalid data;   combine the set of write commands with the invalid data into a write-multi command; and   direct the bus controller to dispatch the write-multi command from the buffer to the NVM.   
     
     
         25 . The system of  claim 21 , wherein the set of write commands comprises encrypted commands. 
     
     
         26 . The system of  claim 25 , further comprising an encryption module, and wherein in response to determining that there is at least one command in the queue with a size equal to the fill size, the control circuitry is operative to:
 direct the encryption module to encrypt the at least one command; and   store the at least one encrypted command in the buffer.