Memory system and integrated management method for plurality of dma channels

Abstract

Provided are a memory system and an integrated management method for a plurality of direct memory access (DMA) channels. The memory system includes a memory controller exchanging data with a memory and having a plurality of channels physically separated from each other, and a DMA controller having a plurality of DMA channels physically separated from each other and in contact with the plurality of channels of the memory controller, and exchanging data with the memory via the plurality of DMA channels and the memory controller.

1 . A memory system, comprising:
 a memory controller exchanging data with a memory and having a plurality of channels physically separated from each other; and   a direct memory access (DMA) controller having a plurality of DMA channels physically separated from each other and in contact with the plurality of channels of the memory controller, and exchanging data with the memory via the plurality of DMA channels and the memory controller.   
     
     
         2 . The memory system of  claim 1 , further comprising a contact module connecting the channels of the memory controller with the DMA channels. 
     
     
         3 . The memory system of  claim 2 , wherein the contact module includes a plurality of buses or a matrix switch for connecting the channels of the memory controller with the DMA channels. 
     
     
         4 . The memory system of  claim 1 , wherein the DMA controller comprises:
 a register module having a set of registers storing information on the exchanged data; and   a multi-channel management module dividing and setting set values for the plurality of DMA channels with reference to the set of registers.   
     
     
         5 . The memory system of  claim 4 , wherein the set of registers includes at least one selected from the group consisting of a source address, a destination address, a transmission size, a source address offset and a destination address offset, and
 the multi-channel management module sets values of source and destination addresses for the plurality of DMA channels by selectively adding or subtracting the values of the source and destination address offsets to or from the values of the source and destination addresses.   
     
     
         6 . The memory system of  claim 4 , wherein the set of registers includes at least one selected from the group consisting of a source address, a destination address, a transmission size, a source address offset and a destination address offset, and
 the multi-channel management module sets a value of a transmission size for the respective DMA channels by dividing the value of the transmission size by the number of the DMA channels.   
     
     
         7 . The memory system of  claim 1 , wherein the memory controller exchanges data with the memory via a memory interface. 
     
     
         8 . The memory system of  claim 1 , wherein the DMA controller further comprises one port for exchanging data with a peripheral device. 
     
     
         9 .- 11 . (canceled)