Highly Reliable NAND Flash memory using a five side enclosed Floating gate storage elements

Abstract

A NAND flash memory system with an array of individual charge storage elements, such as floating gates, arranged in a NAND string, each element being capable of selectively storing data in the form of charge there-in during a program or an erase operation, and during a read operation sensing the quantum of charge stored to provide reconstruction of data. Such a memory made with a floating gate that is spaced away from the diffusions and covered on all five sides except the channel side, by the control gate, there by having increased coupling with the associated advantage of lower high voltages, reduced impact of the unwanted disturb conditions, and providing for improved retention and reliability characteristics at higher operating temperatures is disclosed. The main emphasis in this technology is to provide a device with improved retention, endurance, and temperature characteristics meeting the Automotive specifications even with some area penalty.

1 . A non-Volatile memory cell storage element that is programmed and erased by FN Tunneling comprising:
 a. a first connect diffusion as a source diffusion;   b. a second connect diffusion as a drain diffusion   c. a storage element comprising:
 i. a channel region between the source and drain diffusions; 
 ii. a tunnel dielectric region over a channel region; 
 iii. two high voltage dielectric regions on either side adjacent the tunnel dielectric region over the channel region; 
 iv. a charge storage floating gate deposed over the tunnel dielectric region; 
 v. a dielectric layer covering the floating gate; 
 vi. a conductive control gate deposed over the two high voltage dielectric regions and covering all five sides of the floating gate but separated from it by the dielectric layer covering the floating gate. 
   
     
     
         2 . A non-Volatile NAND Memory cell that is programmed and erased by FN Tunneling comprising:
 a. a drain diffusion;   b. a drain select device adjacent the drain diffusion;   c. a first storage element;   d. a first connect diffusion acting as a source of the drain select device and a drain for the first storage element;   e. a source diffusion;   f. a source select device adjacent the source diffusion;   g. a last storage element;   h. a last connect diffusion acting as a drain of the source select device and a source for the last storage element;   i. a number of storage elements in series with the first and the last storage elements, separated from and interconnected to its neighbor by connect diffusions.   
     
     
         3 . A non-Volatile memory cell storage element that is programmed and erased by FN Tunneling comprising:
 a. a first connect diffusion as a source diffusion;   b. a second connect diffusion as a drain diffusion   c. a storage element comprising:
 i. a channel region between the source and drain diffusions; 
 ii. a tunnel dielectric region over a channel region; 
 iii. two high voltage dielectric regions on either side adjacent the tunnel dielectric region; 
 iv. a charge storage floating gate deposed over the tunnel dielectric region; 
 v. a dielectric layer covering the floating gate; 
 vi. a conductive control gate deposed over the two high voltage dielectric regions and covering all five sides of the floating gate but separated from it by the dielectric layer covering the floating gate; 
 vii. the conductive control gate overlaying the high voltage dielectric and coupling to part of the connect diffusions on either side of the channel.