US2012228722A1PendingUtilityA1

Sram cell with t-shaped contact

Assignee: HOUSTON THEODORE WPriority: Jun 5, 2009Filed: May 25, 2012Published: Sep 13, 2012
Est. expiryJun 5, 2029(~2.9 yrs left)· nominal 20-yr term from priority
Y10S257/903H10W 20/435H10D 89/10H10D 84/0149H10D 84/038H10B 10/00H10B 10/12
48
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Claims

Abstract

An integrated circuit containing an array of SRAM cells with T-shaped contacts in the inverters, in which drain connecting segments may extend beyond gate connecting segments by a distance greater than 10 percent of a separation distance between ends of opposite drain connecting segments. The drain connecting segments may also extend beyond gate connecting segments by a distance greater than one-third of the width of the gate connecting segments. A process of forming an integrated circuit containing an array of SRAM cells with T-shaped contacts in which drain connecting segments may extend beyond gate connecting segments by a distance greater than 10 percent of a separation distance between ends of opposite drain connecting segments. A process may also form the drain connecting segments to extend beyond gate connecting segments by greater than one-third of the width of the gate connecting segments.

Claims

exact text as granted — not AI-modified
1 . An integrated circuit containing an array of SRAM cells, each said SRAM cell comprising:
 a first driver transistor of said SRAM cell of said array within said integrated circuit, said first driver transistor having a drain node and a channel region;   a first load transistor, said first load transistor having a drain node and a channel region;   a first inverter gate, said first inverter gate overlapping said channel region of said first driver transistor and overlapping said channel region of said first load transistor;   a second driver transistor, said second driver transistor having a drain node and a channel region;   a second load transistor, said second load transistor having a drain node and a channel region;   a second inverter gate, said second inverter gate overlapping said channel region of said second driver transistor and overlapping said channel region of said second load transistor;   a first T-shaped contact, further including:
 a first drain connecting segment, said first drain connecting segment overlapping said drain node of said first driver transistor and overlapping said drain node of said first load transistor; and 
 a first gate connecting segment, said first gate connecting segment overlapping said second inverter gate and intersecting said first drain connecting segment; and 
   a second T-shaped contact, further including:
 a second drain connecting segment, said second drain connecting segment overlapping said drain node of said second driver transistor and overlapping said drain node of said second load transistor; and 
 a second gate connecting segment, said second gate connecting segment overlapping said first inverter gate and intersecting said second drain connecting segment, such that; 
 an end of said first drain connecting segment over said drain node of said first load transistor extends beyond said first gate connecting segment by a distance greater than one-third of a width of said first gate connecting segment; and 
 an end of said second drain connecting segment over said drain node of said second load transistor extends beyond said second gate connecting segment by a distance greater than one-third of a width of said second gate connecting segment. 
   
     
     
         2 . The integrated circuit of  claim 1 , in which:
 intersecting edges of said first drain connecting segment and said first gate connecting segment are substantially perpendicular; and   intersecting edges of said second drain connecting segment and said second gate connecting segment are substantially perpendicular.   
     
     
         3 . The integrated circuit of  claim 2 , further including:
 a first passgate transistor, said first passgate transistor having a channel region; and   a second passgate transistor, said second passgate transistor having a channel region, such that;   an outer edge of said channel region of said first passgate transistor extends beyond an outer edge of said channel region of said first driver transistor by a distance greater than half said distance by which said end of said first drain connecting segment extends beyond said first gate connecting segment; and   an outer edge of said channel region of said second passgate transistor extends beyond an outer edge of said channel region of said second driver transistor by a distance greater than half said distance by which said end of said second drain connecting segment extends beyond said second gate connecting segment.

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