Signal generating apparatus for generating power-on-reset signal

Abstract

A signal generating apparatus, for generating a power-on-reset signal, including a bias circuit and a power-on-reset signal generating circuit is disclosed. The bias circuit is for generating an output bias voltage, and includes at least one bipolar junction transistor (BJT), wherein a base terminal of the BJT is coupled to a collector terminal of the BJT, and the output bias voltage is related to an emitter-to-base voltage of the BJT. The power-on-reset signal generating circuit is coupled to the bias circuit, and is for generating a duplicated voltage by duplicating the output bias voltage, wherein the power-on-reset signal is generated according to the duplicated voltage.

1 . A signal generating apparatus for generating a power-on-reset signal, comprising:
 a bias circuit, for generating an output bias voltage, wherein the bias circuit comprises at least one bipolar junction transistor (BJT), a base terminal of the BJT is coupled to a collector terminal of the BJT, and the output bias voltage is related to an emitter-to-base voltage of the BJT; and   a power-on-reset signal generating circuit, for generating a first voltage by substantially duplicating the output bias voltage;   
       wherein the power-on-reset signal is generated according to the first voltage. 
     
     
         2 . The signal generating apparatus of  claim 1 , wherein the power-on-reset signal generating circuit directly outputs the first voltage as the power-on-reset signal. 
     
     
         3 . The signal generating apparatus of  claim 1 , wherein the power-on-reset signal generating circuit comprises:
 a duplication unit, for duplicating the output bias voltage to generate the first voltage; and   a hysteresis unit, coupled to the duplication unit, for receiving the first voltage and generating the power-on-reset signal according to the first voltage.   
     
     
         4 . The signal generating apparatus of  claim 1 , wherein the duplication unit comprises:
 a loading element; and   a current mirror, coupled to the loading element and the bias circuit, for duplicating a current flowing via the bias circuit to generate a duplication current flowing via the loading element, wherein the first voltage is generated according to the duplication current and the loading element.   
     
     
         5 . The signal generating apparatus of  claim 1 , wherein the signal generating apparatus further comprising:
 a bandgap circuit, for generating a reference voltage related to bandgap; and   a determination unit, coupled to the power-on-reset signal generating circuit and the bandgap circuit, for generating the power-on-reset signal according to the reference voltage and the first voltage.   
     
     
         6 . The signal generating apparatus of  claim 5 , wherein the determination unit is an AND gate. 
     
     
         7 . The signal generating apparatus of  claim 5 , wherein the signal generating apparatus further comprises:
 a voltage dividing circuit, for generating a comparison voltage according to a divided voltage of a supply voltage; and   a comparator, for generating a second reference voltage by comparing the reference voltage and the comparison voltage;   
       wherein the determination unit generates the power-on-reset signal according to the second reference voltage and the first voltage. 
     
     
         8 . The signal generating apparatus of  claim 5 , wherein the bandgap circuit comprises a bandgap bias unit having substantially the same circuit structure with the bias circuit. 
     
     
         9 . The signal generating apparatus of  claim 3 , wherein the hysteresis unit is a Schmitt trigger. 
     
     
         10 . The signal generating apparatus of  claim 1 , wherein the bias circuit further comprises at least one metal-oxide-semiconductor (MOS) transistor, agate terminal of the MOS transistor is coupled to a drain terminal of the MOS transistor, a source terminal of the MOS transistor is coupled to the emitter terminal of the BJT, and the output bias voltage generated by the bias circuit comprises an emitter-base voltage of the BJT and a gate-source voltage of the MOS transistor. 
     
     
         11 . A signal generating apparatus for generating a power-on-reset signal, comprising:
 a bias circuit, for generating an output bias voltage according to a bandgap bias circuit; and   a power-on-reset signal generating circuit, for generating a first voltage according to the output bias voltage;   
       wherein the power-on-reset signal is generated according to the first voltage. 
     
     
         12 . The signal generating apparatus of  claim 11 , wherein the power-on-reset signal generating circuit directly outputs the first voltage as the power-on-reset signal. 
     
     
         13 . The signal generating apparatus of  claim 11 , wherein the power-on-reset signal generating circuit comprises:
 a duplication unit, for duplicating the output bias voltage to generate the first voltage; and   a hysteresis unit, coupled to the duplication unit, for receiving the first voltage and generating the power-on-reset signal according to the first voltage.   
     
     
         14 . The signal generating apparatus of  claim 11 , wherein the duplication unit comprises:
 a loading element; and   a current mirror, coupled to the loading element and the bias circuit, for duplicating a current flowing via the bias circuit to generate a duplication current flowing via the loading element, wherein the first voltage is generated according to the duplication current and the loading element.   
     
     
         15 . The signal generating apparatus of  claim 11 , wherein the bias circuit comprises a BJT and a diode-connected MOS.