8T SRAM Cell With One Word Line

Abstract

An integrated circuit with SRAM cells containing dual passgate transistors and a read buffer, all connected to one word line is disclosed. The read buffer and one passgate transistor may be variously configured to a separate read data line and write data line, or a combined data line, in different embodiments. The read buffer in addressed SRAM cells may be biased during read operations. The read buffer in half-addressed SRAM cells may be biased or floated, depending on the configuration of the read data line and the write data line. The read buffer in addressed and half-addressed SRAM cells may be biased or floated, depending on the configuration of the read data line and the write data line.

1 . A process of performing a read operation, comprising:
 biasing a source node of a read buffer driver transistor in an addressed SRAM cell to a potential within a threshold voltage of a potential on source nodes of driver transistors in cross-coupled inverters of said addressed SRAM cell; and   turning on an access transistor in said addressed SRAM cell that is connected to said read buffer driver transistor in an addressed SRAM cell, a bit-side passgate transistor in said addressed SRAM cell, and a bit-bar-side passgate transistor in said addressed SRAM cell through a single word line that is connected to a gate of said access transistor, a gate of said bit-side passgate transistor, and a gate of said bit-bar-side passgate transistor.   
     
     
         2 . The process of  claim 1 , further including applying a half-addressed cell read condition to a source node of a read buffer driver transistor in a half-addressed SRAM cell. 
     
     
         3 . The process of  claim 2 , in which a source/drain node of said bit-side passgate transistor in said addressed SRAM cell is connected to a source/drain node of said access transistor in said addressed SRAM cell plus a bit read line in said addressed SRAM cell. 
     
     
         4 . The process of  claim 2 , in which a source/drain node of said bit-side passgate transistor in said addressed SRAM cell is connected to a bit data line, and a source/drain node of said access transistor in said addressed SRAM cell is connected to a bit read line in said addressed SRAM cell. 
     
     
         5 . The process of  claim 2 , in which a source/drain node of said bit-side passgate transistor in said addressed SRAM cell is connected to a first source/drain node of said access transistor in said addressed SRAM cell, and a second source/drain node of said access transistor in said addressed SRAM cell is connected to a bit data line in said addressed SRAM cell. 
     
     
         6 . A process of performing a write operation, comprising:
 applying an addressed cell write condition to a source node of a read buffer driver transistor in an addressed SRAM cell; and   turning on an access transistor in said addressed SRAM cell that is connected to said read buffer driver transistor in said addressed SRAM cell, a bit-side passgate transistor in said addressed SRAM cell, and a bit-bar-side passgate transistor in said addressed SRAM cell through a single word line that is connected to a gate of said access transistor, a gate of said bit-side passgate transistor, and a gate of said bit-bar-side passgate transistor.   
     
     
         7 . The process of  claim 6 , further including applying a half-addressed cell write condition to a source node of a read buffer driver transistor in a half-addressed SRAM cell. 
     
     
         8 . The process of  claim 7 , in which a source/drain node of said bit-side passgate transistor in said addressed SRAM cell is connected to a source/drain node of said access transistor in said addressed SRAM cell plus a bit read line in said addressed SRAM cell. 
     
     
         9 . The process of  claim 7 , in which a source/drain node of said bit-side passgate transistor in said addressed SRAM cell is connected to a bit data line, and a source/drain node of said access transistor in said addressed SRAM cell is connected to a bit read line in said addressed SRAM cell. 
     
     
         10 . The process of  claim 7 , in which a source/drain node of said bit-side passgate transistor in said addressed SRAM cell is connected to a first source/drain node of said access transistor in said addressed SRAM cell, and a second source/drain node of said access transistor in said addressed SRAM cell is connected to a bit data line in said addressed SRAM cell. 
     
     
         11 . A process of transitioning to standby mode, comprising:
 turning off an access transistor in SRAM cell that is connected to a read buffer driver transistor in said SRAM cell, a bit-side passgate transistor in said SRAM cell, and a bit-bar-side passgate transistor in said SRAM cell through a single word line that is connected to a gate of said access transistor, a gate of said bit-side passgate transistor, and a gate of said bit-bar-side passgate transistor; and   floating a source node of said read buffer driver transistor in said SRAM cell to a potential within a threshold voltage of a potential on source nodes of driver transistors in cross-coupled inverters of said SRAM cell.