US2012235979A1PendingUtilityA1

Liquid crystal display sub-pixel with three different voltage levels

54
Assignee: SHIBAZAKI MINORUPriority: Mar 21, 2008Filed: Mar 28, 2012Published: Sep 20, 2012
Est. expiryMar 21, 2028(~1.7 yrs left)· nominal 20-yr term from priority
G09G 2310/0262G09G 2320/0233G09G 3/3648G02F 1/13624G09G 2300/0456
54
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

This present invention provides a liquid crystal display (LCD) device in which the sub-pixel is provided with three different voltage levels, so that image quality is improved without the configuration of additional gate lines. The present invention overcomes the reduction of aperture ratio in conventional LCD devices due to the configuration of additional gate lines. By the present invention, the white washout problem relating to the off-axis viewing angle can be overcome while the aperture ratio is not reduced.

Claims

exact text as granted — not AI-modified
1 - 8 . (canceled) 
     
     
         9 . An electronic device, comprising:
 a liquid crystal display (LCD) device, comprising:   a source line;   an n-th gate line;   an n+1-th gate line; and   a sub-pixel of the n-th row, said sub-pixel comprising a first semiconductor switch, a second semiconductor switch, a third semiconductor switch, a fourth semiconductor switch, a first pixel electrode, a second pixel electrode, a third pixel electrode and a fourth pixel electrode;   wherein said first semiconductor switch is electrically connected to said n-th gate line, said source line and said first pixel electrode, said n-th gate line enabling said source line and said first pixel electrode by switching on said first semiconductor switch; said second semiconductor switch is electrically connected to said n+1-th gate line, said first pixel electrode and said second pixel electrode, said n+1-th gate line enabling said first pixel electrode and said second pixel electrode by switching on said second semiconductor switch; said third semiconductor switch is electrically connected to said n-th gate line, said first pixel electrode and said third pixel electrode, said n-th gate line enabling said first pixel electrode and said third pixel electrode by switching on said third semiconductor switch; said fourth semiconductor switch is electrically connected to said n-th gate line, said second pixel electrode and said fourth pixel electrode, said n-th gate line enabling said second pixel electrode and said fourth pixel electrode by switching on said fourth semiconductor switch; and   wherein after a data-writing period of the n-th row, said second pixel electrode and said fourth pixel electrode have a first voltage level, while said first pixel electrode and said third pixel electrode have a second voltage level; and during a data-writing period of the n+1-th row, said n+1-th gate line enables said first pixel electrode and said second pixel electrode by switching on said second semiconductor switch so as to provide said first pixel electrode and said second pixel electrode with a third voltage level respectively.   
     
     
         10 . A method for driving an LCD device, comprising the steps of:
 electrically connecting a first semiconductor switch with a n-th gate line, a source line and a first pixel electrode;   switching on said first semiconductor switch by said n-th gate line to enable said source line and said first pixel electrode;   electrically connecting a second semiconductor switch with a n+1-th gate line, said first pixel electrode and a second pixel electrode;   switching on said second semiconductor switch by said n+1-th gate line to enable said first pixel electrode and said second pixel electrode;   electrically connecting a third semiconductor switch with said n-th gate line, said first pixel electrode and a third pixel electrode;   switching on said third semiconductor switch by said n-th gate line to enable said first pixel electrode and said third pixel electrode;   electrically connecting a fourth semiconductor switch with said n-th gate line, said second pixel electrode and a fourth pixel electrode;   switching on said fourth semiconductor switch by said n-th gate line to enable said second pixel electrode and said fourth pixel electrode;   after a data-writing period of the n-th row, providing a first voltage level to said second pixel electrode and said fourth pixel electrode, and providing a second voltage level to said first pixel electrode and said third pixel electrode; and   during a data-writing period of the n+1-th row, enabling said first pixel electrode and said second pixel electrode by said n+1-th gate line through switching on said second semiconductor switch so as to provide a third voltage level respectively to said first pixel electrode and said second pixel electrode.

Cited by (0)

No later patents cite this yet.

References (0)

No backward citations on record.