Non-volatile memory with error correction for page copy operation and method thereof

Abstract

The disclosure is a NAND flash memory with the function of error checking and correction during a page copy operation. The NAND flash memory is able to prohibit transcription of erroneous bits to a duplicate page from a source page. Embodiments of the inventive flash memory include a correction circuit for correcting bit errors of source data stored in a page buffer, a circuit configured to provide the source data to the correction circuit and to provide correction data to the page buffer, and a copy circuit configured to copy the source data to the page buffer, and to store the correction data in the other page from the page buffer.

1 . A nonvolatile memory comprising:
 a plurality of pages storing data;   a page buffer temporarily storing data by the page;   a correction circuit for correcting a bit error of source data of a specific one of the pages;   a transferring circuit configured to provide the source data to the correction circuit from the page buffer and to provide amended data to the page buffer from the correction circuit after the correction circuit has corrected the bit error; and   a replicating circuit configured to copy the source data into the page buffer and to store the amended data into another page from the page buffer;   wherein:
 the source data contains old parities; 
 the correction circuit for generating new parities from the source data, and compares the new parities with the old parities; 
 the correction circuit comprises a circuit for generating column parities for bits composing one byte of the source data; and a circuit for generating line parities for bytes of the source data; and 
 for a one bit error in the source data, the line parities indicate a binary weighted line address and its complement of the one bit error in the page buffer, and the column parities indicate a binary weighted column address and its complement of the one bit error in the page buffer. 
   
     
     
         2 . The nonvolatile memory of  claim 1 , wherein the nonvolatile memory is a NAND flash memory. 
     
     
         3 . A nonvolatile memory comprising:
 a data field composed of a plurality of pages for storing data;   a first storage configured to store first parities in a predetermined region of the data field, the first parities being generated during a programming operation for the page;   a page buffer for temporarily storing data by the page;   a moving circuit configured to copy source data stored in a first one of the pages into the page buffer;   a parity circuit configured to generate second parities from the source data stored in the page buffer;   a correction circuit configured to generate modified data from the source data in response to a result of comparing the first parities with the second parities; and   a transfer circuit configured to transfer the modified data of the source data to the page buffer;   wherein:
 the moving circuit is further configured to copy the modified data in the page buffer to a second one of the pages after the correction circuit has generated the modified data; 
 the parity circuit comprises a circuit for generating column parities for bits composing one byte of the source data; and a circuit for generating line parities for bytes of the source data; and 
 for a one bit error in the source data, the line parities indicate a binary weighted line address and its complement of the one bit error in the page buffer, and the column parities indicate a binary weighted column address and its complement of the one bit error in the page buffer. 
   
     
     
         4 . The nonvolatile memory of  claim 3 , wherein the second parities comprise column parities and line parities. 
     
     
         5 . The nonvolatile memory of  claim 4 , wherein the parity circuit comprises a circuit for generating column parities for bits composing one byte of the source data; and a circuit for generating line parities for bytes of the source data. 
     
     
         6 . The nonvolatile memory of  claim 3 , wherein the nonvolatile memory is a NAND flash memory. 
     
     
         7 . A method of transferring source data of a first page to a second page in a nonvolatile memory having a page buffer structured to temporarily store data by the page, the source data containing old parities, the method comprising:
 storing the source data from the first page into the page buffer;   generating new parities from the source data stored in the page buffer;   comparing the old parities with the new parities;   creating modified data from the source data in response to a result of the comparing;   moving the modified data to the page buffer after the creation of the modified data; and   storing the modified data in the page buffer in the second page;   wherein:
 storing the source data into the page buffer further comprises storing the source data into a plurality of lines and a plurality of columns of the page buffer; and 
 generating new parities from the source data stored in the page buffer further comprises generating the new parities including:
 a plurality of pairs of line parities, for each line parity pair, a first line parity associated with a first half of the lines, and a second line parity associated with a second half of the lines; and 
 a plurality of pairs of column parities, for each column parity pair, a first column parity of the pair associated with a first half of the columns, and a second column parity of the pair associated with a second half of the columns; 
 wherein for a one bit error in the source data, the line parities indicate a binary weighted line address and its complement of the one bit error in the page buffer, and the column parities indicate a binary weighted column address and its complement of the one bit error in the page buffer. 
 
   
     
     
         8 . The method of  claim 7 , further comprising storing the old parities of the source data into a predetermined field of the memory before storing the source data into the page buffer. 
     
     
         9 . The method of  claim 7 , further comprising informing an error status by the comparing result of the outside of the memory.