Performance In A Virtualization Architecture With A Processor Abstraction Layer

Abstract

Embodiments of apparatuses and methods for improving performance in a virtualization architecture are disclosed. In one embodiment, an apparatus includes a processor and a processor abstraction layer. The processor abstraction layer includes instructions that, when executed by the processor, support techniques to improve the performance of the apparatus in a virtualization architecture.

1 . An apparatus comprising:
 a processor including a storage to store a processor abstraction layer (“PAL”) including service instructions, accessible to the processor as a PAL service without a decode operation, to determine a function to be performed without performance of a parameter checking operation and a processor state checking operation.   
     
     
         2 . The apparatus of  claim 1 , wherein the storage is to further store PAL procedure instructions, accessible to the processor as a PAL procedure with a decode operation, to determine a first function to be performed with the parameter checking operation and with the processor state checking operation. 
     
     
         3 . The apparatus of  claim 1 , wherein the PAL service instructions, when executed by the processor, support at least one technique to improve performance of the apparatus in a virtualization architecture. 
     
     
         4 . The apparatus of  claim 1 , wherein the storage is also to store a PAL service jump table. 
     
     
         5 . The apparatus of  claim 4 , wherein the PAL service jump table includes an offset value, and the PAL service is accessible to the processor by execution of an instruction to branch to a memory location addressable as a base address plus the offset value. 
     
     
         6 . The apparatus of  claim 1 , wherein the processor includes circuitry to support virtualization of a hardware resource. 
     
     
         7 . The apparatus of  claim 6 , wherein the circuitry comprises a shadow register to shadow attempts to access an architectural register. 
     
     
         8 . The apparatus of  claim 7 , wherein the storage is to store synchronization instructions that, when executed by the processor, synchronize the values in the shadow register with the values in a virtual register corresponding to the architectural register. 
     
     
         9 . A method comprising:
 initializing a virtualization environment in a virtualization architecture;   performing a parameter checking operation and a processor state checking operation in connection with calling a procedure instruction in a processor executing instructions of a processor abstraction layer (“PAL”) stored in a storage;   performing a decode operation, in response to calling the procedure instruction, to determine a first function to be performed; and   calling a service instruction in the PAL without a decode operation to determine a second function to be performed without the parameter checking operation and without the processor state checking operation.   
     
     
         10 . The method of  claim 9 , further comprising passing a base address to a caller of the procedure instruction. 
     
     
         11 . The method of  claim 9 , further comprising executing the service instruction to synchronize a hardware resource to support virtualization with a virtual resource. 
     
     
         12 . The method of  claim 11 , wherein the hardware resource is a shadow register and the virtual resource is a virtualized copy of an architectural register. 
     
     
         13 . The method of  claim 9 , further comprising determining whether the service instruction is to be executed based on an indicator. 
     
     
         14 . The method of  claim 13 , wherein the indicator is based on an enable indicator that indicates whether a virtualization technique is enabled. 
     
     
         15 . The method of  claim 14 , wherein the indicator is based on a selection indicator that indicates whether the service instruction is selected. 
     
     
         16 . An apparatus comprising:
 a processor to load an optimization template made available via a processor abstraction layer (“PAL”), the optimization template including an indicator to indicate whether a virtualization event is to be handled by a virtual machine monitor (VMM) of a virtualization environment and if so to transfer control to the VMM, and otherwise to continue execution via the PAL, wherein the execution is continue via the PAL without the control transfer to the VMM.   
     
     
         17 . The apparatus of  claim 16 , wherein the processor is to perform a parameter checking operation and a processor state checking operation in connection with a call to a procedure instruction. 
     
     
         18 . The apparatus of  claim 17 , wherein the processor is to perform a decode operation, in response to the call to the procedure instruction, to determine a first function to be performed. 
     
     
         19 . The apparatus of  claim 18 , wherein the processor is to call a service instruction in the PAL without a decode operation to determine a second function to be performed without the parameter checking operation and without the processor state checking operation.