Trench-gate ldmos structures

Abstract

MOSFET devices for RF applications that use a trench-gate in place of the lateral gate conventionally used in lateral MOSFET devices. A trench-gate provides devices with a single, short channel for high frequency gain. Embodiments of the present invention provide devices with an asymmetric oxide in the trench gate, as well as LDD regions that lower the gate-drain capacitance for improved RF performance. Refinements to these TG-LDMOS devices include placing a source-shield conductor below the gate and placing two gates in a trench-gate region. These improve device high-frequency performance by decreasing gate-to-drain capacitance. Further refinements include adding a charge balance region to the LDD region and adding source-to-substrate or drain-to-substrate vias.

1 . An apparatus, comprising:
 a first silicon region of a first conductivity type, the first silicon region having a surface;   a gate-trench region extending from the surface of the first silicon region into the first silicon region, the gate trench region comprising:
 a source-shield region comprising a first conductive region; 
 a gate region comprising a second conductive region and between the surface of the first silicon region and the source-shield region, the gate-trench region having an asymmetric insulating layer along two of its opposing sidewalls; 
   a source region comprising a dopant region of a second conductivity type, the dopant region laterally extending along one side of the gate trench region and contacting a source electrode; and   a lightly-doped drain region of the second conductivity type laterally extending below and along an opposing side of the one side of the gate trench region and contacting a drain electrode.   
     
     
         2 . The apparatus of  claim 1 , wherein the source-shield region is between the gate region and the lightly-doped drain region. 
     
     
         3 . The apparatus of  claim 1 , wherein the source-shield region is a polysilicon region. 
     
     
         4 . The apparatus of  claim 1 , wherein the source-shield region and gate regions are polysilicon regions. 
     
     
         5 . The apparatus of  claim 1 , wherein the lightly doped drain region partially extends along a first sidewall of the gate trench such that a channel region along the first sidewall between the source region and the lightly doped drain region extends along the vertical dimension. 
     
     
         6 . The apparatus of  claim 1 , further comprising:
 a charge-balance region of the first conductivity type, the charge-balance region in the lightly-doped drain region.   
     
     
         7 . The apparatus of  claim 1 , wherein the first silicon region is an epitaxial layer formed on a substrate, the MOSFET further comprising:
 a source-substrate via coupling the source to the substrate.   
     
     
         8 . The apparatus of  claim 1 , wherein the first silicon region is an epitaxial layer formed on a substrate, the MOSFET further comprising:
 a drain-substrate via coupling the source to the substrate.   
     
     
         9 . An apparatus, comprising:
 a first silicon region of a first conductivity type, the first silicon region having a surface;   a gate-trench region extending from the surface of the first silicon region into the first silicon region, the gate trench region comprising:
 a first gate region comprising a first conductive region; 
 a second gate region comprising a second conductive region and between the surface of the first silicon region and the first gate region, the gate-trench region having an asymmetric insulating layer along two of its opposing sidewalls; 
   a source region comprising a dopant region of a second conductivity type, the dopant region laterally extending along one side of the gate trench region and contacting a source electrode; and   a lightly-doped drain region of the second conductivity type laterally extending below and along an opposing side of the one side of the gate trench region and contacting a drain electrode.   
     
     
         10 . The apparatus of  claim 9 , wherein the first gate region is between the second gate region and the lightly-doped drain region. 
     
     
         11 . The apparatus of  claim 9 , wherein the first and second gate regions are polysilicon regions. 
     
     
         12 . The apparatus of  claim 9 , wherein the lightly doped drain region partially extends along a first sidewall of the gate trench such that a channel region along the first sidewall between the source region and the lightly doped drain region extends along the vertical dimension. 
     
     
         13 . The apparatus of  claim 9 , further comprising:
 a charge-balance region of the first conductivity type, the charge-balance region in the lightly-doped drain region.   
     
     
         14 . The apparatus of  claim 9 , wherein the first silicon region is an epitaxial layer formed on a substrate, the MOSFET further comprising:
 a source-substrate via coupling the source to the substrate.   
     
     
         15 . The apparatus of  claim 9 , wherein the first silicon region is an epitaxial layer formed on a substrate, the MOSFET further comprising:
 a drain-substrate via coupling the source to the substrate.   
     
     
         16 . An apparatus, comprising:
 a first silicon region of a first conductivity type, the first silicon region having a surface;   a gate-trench region extending from the surface of the first silicon region into the first silicon region, the gate trench region including a gate region comprising a conductive region, the gate-trench region also including an asymmetric insulating layer along two of its opposing sidewalls;   a source region comprising a dopant region of a second conductivity type, the dopant region laterally extending along one side of the gate trench region and contacting a source electrode; and   a lightly-doped drain region of the second conductivity type laterally extending below and along an opposing side of the one side of the gate trench region and contacting a drain electrode, the lightly-doped drain region comprising a charge-balance region of the first conductivity type.   
     
     
         17 . The apparatus of  claim 16 , wherein the charge-balance region is between the gate-trench region and the drain electrode. 
     
     
         18 . The apparatus of  claim 17 , wherein the first silicon region is an epitaxial layer formed on a substrate, the MOSFET further comprising:
 a source-substrate via coupling the source to the substrate.   
     
     
         19 . The apparatus of  claim 17 , wherein the first silicon region is an epitaxial layer formed on a substrate, the MOSFET further comprising:
 a drain-substrate via coupling the source to the substrate.   
     
     
         20 . The apparatus of  claim 17 , wherein the lightly doped drain region partially extends along a first sidewall of the gate trench such that a channel region along the first sidewall between the source region and the lightly doped drain region extends along the vertical dimension.