Field effect transistor, and electric circuit

Abstract

The invention relates to a field effect transistor comprising at least one source electrode layer and at least one drain electrode layer arranged in the same plane, a semiconductor layer, an insulator layer and a gate electrode layer, wherein the gate electrode layer, as seen perpendicular to the plane of the at least one source electrode layer and the at least one drain electrode layer, only partly covers a channel arranged between the at least one source electrode layer and the at least one drain electrode layer.

1 . A field effect transistor ( 1 ,  1 ′,  1 ″,  1 ′″) comprising at least one source electrode layer ( 2 ) and at least one drain electrode layer ( 3 ,  3   a ,  3   b ,  3   c ,  3   d ) arranged in the same plane, a semiconductor layer ( 5 ), an insulator layer ( 6 ) and a gate electrode layer ( 4 ),
 characterized 
 in that the gate electrode layer ( 4 ), as seen perpendicular to the plane of the at least one source electrode layer ( 2 ) and the at least one drain electrode layer ( 3 ,  3   a ,  3   b ,  3   c ,  3   d ), only partly covers a channel ( 7 ) arranged between the at least one source electrode layer ( 2 ) and the at least one drain electrode layer ( 3 ,  3   a ,  3   b ,  3   c ,  3   d ). 
 
     
     
         2 . The field effect transistor as claimed in  claim 1 ,
 characterized   in that the channel ( 7 ) extends between the at least one source electrode layer ( 2 ) and at least two drain electrode layers ( 3   a ,  3   b ,  3   c ,  3   d ), wherein the drain electrode layers ( 3   a ,  3   b ,  3   c ,  3   d ) are embodied in a manner electrically insulated from one another.   
     
     
         3 . The field effect transistor as claimed in either of  claims 1  and  2 ,
 characterized 
 in that the gate electrode layer ( 4 ), as seen perpendicular to the plane of the at least one source electrode layer ( 2 ) and the at least one drain electrode layer ( 3 ,  3   a ,  3   b ,  3   c ,  3   d ), covers an area of 10 to 90%, in particular of 25 to 50%, of the channel ( 7 ). 
 
     
     
         4 . The field effect transistor as claimed in any of  claims 1  to  3 ,
 characterized 
 in that the gate electrode layer ( 4 ) is embodied as a bottom gate electrode or as a top gate electrode. 
 
     
     
         5 . The field effect transistor as claimed in any of  claims 1  to  4 ,
 characterized 
 in that the field effect transistor ( 1 ,  1 ′,  1 ″,  1 ′″) comprises at least one organic functional layer. 
 
     
     
         6 . The field effect transistor as claimed in  claim 5 ,
 characterized   in that at least one organic functional layer is formed by printing.   
     
     
         7 . The field effect transistor as claimed in either of  claims 5  and  6 ,
 characterized 
 in that the semiconductor layer ( 5 ) and/or the insulator layer ( 6 ) are/is embodied as an organic functional layer. 
 
     
     
         8 . The field effect transistor as claimed in any of  claims 1  to  7 ,
 characterized 
 in that the source electrode layer ( 2 ), the at least one drain electrode layer ( 3 ,  3   a ,  3   b ,  3   c ,  3   d ), the semiconductor layer ( 5 ), the insulator layer ( 6 ) and the gate electrode layer ( 4 ) are arranged on a carrier substrate ( 10 ). 
 
     
     
         9 . The field effect transistor as claimed in  claim 8 ,
 characterized   in that the carrier substrate ( 10 ) is formed from a flexible plastic film, in particular from polyester, polyethylene, polyethylene terephthalate or polyimide.   
     
     
         10 . A logic component having at least one field effect transistor ( 1 ,  1 ′,  1 ″,  1 ′″) as claimed in any of  claims 1  to  9 . 
     
     
         11 . The logic component as claimed in  claim 10 ,
 characterized   in that the logic component is a structural element from the group comprising inverter components ( 100 ,  100 ′,  101 ,  101 ′), NOR gates, NAND gates, AND gates and OR gates.   
     
     
         12 . The logic component as claimed in  claim 11 ,
 characterized   in that the logic component is an inverter component ( 100 ,  100 ′,  101 ,  101 ′) comprising a field effect transistor ( 1 ,  1 ′,  1 ″,  1 ′″) and at least one charging component ( 9 ,  9 ′,  9 ″,  9   a ,  9   b ,  9   a ′,  9   b ′) having at least one first electrode ( 12 ,  12 ′,  12 ″,  12   a ,  12   b ,  12   a ′,  12   b ′) and at least one second electrode ( 13 ,  13 ′,  13 ″,  13   a ,  13   b ,  13   a ′,  13   b ′), wherein the at least one second electrode ( 13 ,  13 ′,  13 ″,  13   a ,  13   b ,  13   a ′,  13   b ′) is embodied for connection to a supply voltage, and wherein at least one of the first electrodes ( 12 ,  12 ′,  12 ″,  12   a ,  12   b ,  12   a ′,  12   b ′) is electrically conductively connected to at least one drain electrode layer ( 3 ,  3   a ,  3   b ,  3   c ,  3   d ) of the field effect transistor ( 1 ,  1 ′,  1 ″,  1 ′″) which, as seen perpendicular to the plane of the at least one source electrode layer ( 2 ) and the at least one drain electrode layer ( 3 ,  3   a ,  3   b ,  3   c ,  3   d ), overlaps the gate electrode layer ( 4 ) at least in regions.   
     
     
         13 . The logic component as claimed in  claim 12 ,
 characterized   in that the electrically conductive connection between the at least one first electrode ( 12 ,  12 ′,  12 ″,  12   a ,  12   b ,  12   a ′,  12   b ′) and the at least one drain electrode layer ( 3 ,  3   a ,  3   b ,  3   c ,  3   d ) of the field effect transistor ( 1 ,  1 ′,  1 ′″) is formed by at least one interconnect ( 11 ,  11 ′,  11 ″) and/or at least one via ( 11   a ,  11   a ′,  11   a ″).   
     
     
         14 . The logic component as claimed in either of  claims 12  and  13 ,
 characterized 
 in that the inverter component ( 100 ,  100 ′,  101 ,  101 ′) comprises a field effect transistor ( 1 ,  1 ′,  1 ″,  1 ′″) having at least one source electrode layer ( 2 ) and at least two drain electrode layers ( 3   a ,  3   b ,  3   c ,  3   d ) and also comprises at least two charging components ( 9 ′,  9 ″,  9   a ,  9   b ,  9   a ′,  9   b ′) having at least two first electrodes ( 12 ′,  12 ″,  12   a ,  12   b ,  12   a ′,  12   b ′), wherein a respective one of the drain electrode layers ( 3   a ,  3   b ,  3   c ,  3   d ) is electrically conductively connected to a respective one of the first electrodes ( 12 ′,  12 ″,  12   a ,  12   b ,  12   a ′,  12   b ′). 
 
     
     
         15 . An electric circuit comprising at least one logic component as claimed in any of  claims 10  to  14 . 
     
     
         16 . The electric circuit as claimed in  claim 15 ,
 characterized   in that the electric circuit comprises at least two inverter components ( 100 ,  100 ′,  101 ,  101 ′).   
     
     
         17 . The electric circuit as claimed in  claim 16 ,
 characterized   in that a first inverter component ( 100 ,  101 ) has a first gate electrode layer, and in that the first gate electrode layer is electrically conductively connected to the at least one interconnect ( 11 ″) and/or the at least one via ( 11   a ″) of a second inverter component ( 100 ′,  101 ′) which, as claimed in  claim 13 , electrically conductively connects the at least one drain electrode layer and the at least one first electrode ( 12 ″,  12   b ′) of the charging component ( 9 ″,  9   b ′) of the second inverter component ( 100 ′,  101 ′).   
     
     
         18 . The electric circuit as claimed in  claim 17 ,
 characterized   in that the at least one interconnect ( 11 ″) is arranged on the plane of the at least one source electrode layer ( 2 ) and the at least one drain electrode layer ( 3 ,  3   a ,  3   b ,  3   c ,  3   d ), and in that the first gate electrode layer and the at least one interconnect ( 11 ″) are electrically conductively connected to one another by means of at least one via ( 11   a ″) in the semiconductor layer ( 5 ) and the insulator layer ( 6 ).   
     
     
         19 . The electric circuit as claimed in  claim 17 ,
 characterized   in that the first gate electrode layer, as claimed in  claim 13 , is electrically conductively connected to the at least one drain electrode layer and the at least one first electrode ( 12   b ′) of the second inverter component ( 101 ′) by means of at least one via ( 11   a ″) in the semiconductor layer ( 5 ) and the insulator layer ( 6 ).   
     
     
         20 . An electric circuit, more particularly as claimed in any of  claims 15  to  19 , on a carrier substrate ( 10 ), wherein at least one first component and at least one second component, which are electrically conductively connected to one another, are formed on the carrier substrate ( 10 ),
 characterized 
 in that at least two second components are formed, in that an electrically conductive functional layer of the first component is electrically conductively connected to an electrically conductive functional layer of one of the at least two second components by means of a printed interconnect, wherein the at least one first component is alternatively connected to one or the other of the at least two second components and at least one unused, surplus second component is thus present. 
 
     
     
         21 . The electric circuit as claimed in  claim 20 ,
 characterized   in that the at least two second components are arranged one after another and adjacent to one another in the printing direction of the interconnect.   
     
     
         22 . The electric circuit as claimed in either of  claims 20  and  21 ,
 characterized 
 in that at least two first components are formed, and in that one of the first components is electrically conductively connected to one of the second components by means of the interconnect, such that at least one first component and at least one second component are present in unused and surplus fashion. 
 
     
     
         23 . The electric circuit as claimed in  claim 22 ,
 characterized   in that the at least two first components are arranged one after another and adjacent to one another as seen in the printing direction of the interconnect.   
     
     
         24 . The electric circuit as claimed in any of  claims 20  to  23 ,
 characterized 
 in that a field effect transistor ( 1 ′,  1 ″,  1 ′″) as claimed in any of  claims 1  to  9  is embodied as first component, said transistor having at least one drain electrode layer as electrically conductive functional layer. 
 
     
     
         25 . The electric circuit as claimed in  claim 24 ,
 characterized   in that a charging component ( 9   a ,  9   b ;  9   a ′,  9   b ′) having at least one first electrode ( 12   a ,  12   b ,  12   a ′,  12   b ′) as electrically conductive functional layer and at least one second electrode ( 13   a ,  13   b ,  13   a ′,  13   b ′) is embodied as second component, wherein the at least one second electrode ( 13   a ,  13   b ,  13   a ′,  13   b ′) is embodied for connection to a supply voltage.   
     
     
         26 . A method for producing an electric circuit, more particularly as claimed in any of  claims 20  to  25 , on a carrier substrate ( 10 ), wherein at least one first component and at least one second component, which are electrically conductively connected to one another, are formed on the carrier substrate ( 10 ),
 characterized 
 in that at least two second components are formed, in that an electrically conductive functional layer of the first component is electrically conductively connected to an electrically conductive functional layer of one of the at least two second components by printing an interconnect, wherein the at least one first component, depending on the register tolerance during the printing of the interconnect, is alternatively connected to one or the other of the at least two second components and at least one second component thus remains unused. 
 
     
     
         27 . The method as claimed in  claim 26 ,
 characterized   in that the at least two second components are arranged one after another and adjacent to one another as seen in the printing direction of the interconnect.   
     
     
         28 . The method as claimed in either of  claims 26  and  27 ,
 characterized 
 in that at least two first components are formed, and in that one of the first components is electrically conductively connected to one of the second components by means of the interconnect, such that at least one first component and at least one second component remain unused. 
 
     
     
         29 . The method as claimed in  claim 28 ,
 characterized   in that the at least two first components are arranged one after another and adjacent to one another as seen in the printing direction of the interconnect.