Method for indicating a non-flash nonvolatile multiple-type three-dimensional memory

Abstract

Circuitry and a method for indicating a multiple-type memory is disclosed. The multiple-type memory includes memory blocks in communication with control logic blocks. The memory blocks and the control logic blocks are configured to emulate a plurality of memory types. The memory blocks can be configured into a plurality of vertically stacked memory planes. The vertically stacked memory planes may be used to increase data storage density and/or the number of memory types that can be emulated by the multiple-type memory. Each memory plane can emulate one or more memory types. The control logic blocks can be formed in a substrate (e.g., a silicon substrate including CMOS circuitry) and the memory blocks or the plurality of memory planes can be positioned over the substrate and in communication with the control logic blocks. The multiple-type memory may be non-volatile so that stored data is retained in the absence of power.

1 . A device comprising:
 a silicon semiconductor substrate, the substrate including active circuitry fabricated on a logic plane of the substrate;   the active circuitry including a plurality of control logic blocks, each logic block arranged to provide control and interface functions for at least one corresponding memory block;   a plurality of non-Flash, nonvolatile multiple-type memories, formed among a plurality of vertically stacked memory planes that are in contact with one another and are fabricated above the substrate;   the multiple-type memories configurable into a plurality of memory blocks;   wherein each memory block and its associated control logic block are isolated from the other memory blocks and control logic blocks so as to function as separate and independent memory devices; and   wherein each memory block and its associated control logic block are configured to function as a single memory type;   at least one of the control logic blocks including decode logic, the decode logic arranged to receive a memory address, and to decode the memory address to a memory select value based on a memory select parameter, the memory select value being configured to indicate one of the plurality of multiple-type memories; and   the control logic further configured to output the memory select value if the memory address decodes to the memory select value, and to output a non-select value if the memory address decodes to a value that is different from the memory select value.