Sram cell with asymmetrical pass gate

Abstract

A method of controlling gate induced drain leakage current of a transistor is disclosed. The method includes forming a dielectric region ( 516 ) on a surface of a substrate having a first concentration of a first conductivity type (P-well). A gate region ( 500 ) having a length and a width is formed on the dielectric region. Source ( 512 ) and drain ( 504 ) regions having a second conductivity type (N+) are formed in the substrate on opposite sides of the gate region. A first impurity region ( 508 ) having the first conductivity type (P+) is formed adjacent the source. The first impurity region has a second concentration greater than the first concentration.

1 . An SRAM memory cell, comprising:
 a storage node of the SRAM memory cell;   a bitline node of the SRAM memory cell; and   an asymmetrical access transistor connected between the storage node and bitline node of the SRAM memory cell, wherein the asymmetrical access transistor has a first threshold voltage when said storage node is positive with respect to the bitline node and said asymmetrical access transistor has a second threshold voltage of greater magnitude than the first threshold voltage when the storage node is negative with respect to the bitline node.   
     
     
         2 . The SRAM memory cell of  claim 1 , wherein a difference between said second threshold voltage and said first threshold voltage is approximately 100 mV. 
     
     
         3 . The SRAM memory cell of  claim 1 , wherein the asymmetrical access transistor includes a pocket implant region on a storage node side. 
     
     
         4 . The SRAM memory cell of  claim 3 , wherein said asymmetrical access transistor comprises a source region and a drain region of a first conductivity type and wherein said pocket implant region is of a second conductivity type, opposite said first conductivity type.