Data processing circuit

Abstract

The present invention provides a functional block that executes video coding and video decoding based on H. 264/AVC. The functional block includes two moving picture processing units, and a memory unit that stores therein data related to the results of processing of first plural macroblocks arranged within one row of one picture by the first moving picture processing unit. Data related to the results of processing of plural adjacent macroblocks, which are selected from the data stored in the memory unit, are transferred to the second moving picture processing unit. The second moving picture processing unit performs processing of one macroblock of second plural macroblocks arranged in the following row, using the transferred data.

1 - 26 . (canceled) 
     
     
         27 . A functional block capable of executing at least any one of video coding and video decoding based on H. 264/AVC, comprising:
 at least a first moving picture processing unit and a second moving picture processing unit capable of parallel operations, and   a memory unit which is coupled to the first moving picture processing unit and the second moving picture processing unit and stores therein data related to results of processing by the first moving picture processing unit,   wherein, when the first moving picture processing unit and the second moving picture processing unit perform the parallel operations, a data processing unit processed by each of the first moving picture processing unit and the second moving picture processing unit includes macroblocks having a plurality of sample numbers,   wherein each of the first moving picture processing unit and the second moving picture processing unit includes pipeline connections of a plurality of functional subunits operated with timings different from one another in function and different in pipeline operation so as to execute a selected one of the video coding and the video decoding,   wherein the function block is operative to processes a coded frame picture,   wherein, when the functional block processes the coded frame picture, the first moving picture processing unit processes as data units respective sets of macroblock pairs of same rows in first plural macroblocks arranged within one row of one picture and second plural macroblocks arranged within a first succeeding row located immediately after the one row, and the second moving picture processing unit processes as data units respective sets of macroblock pairs of same rows in third plural macroblocks arranged within a second succeeding row located immediately after the first succeeding row, and fourth plural macroblocks arranged within a third succeeding row located immediately after the second succeeding row, and the timing to start the pipeline operation of the second moving picture processing unit is delayed by four or more time slots of the pipeline operation from the timing to start the pipeline operation of the first moving picture processing unit, and   wherein the data related to the results of processing of at least the plural adjacent macroblocks by the first moving picture processing unit are transferred from the memory unit to the second moving picture processing unit prior to the start of processing for the intra-frame prediction for the processing of the one macroblock by the second moving picture processing unit.   
     
     
         28 . The functional block according to  claim 27 ,
 wherein a result of processing of one macroblock of the plural adjacent macroblocks is selected in accordance with a prediction mode used for the intra-frame prediction of the one macroblock from the data related to the results of processing of the plural adjacent macroblocks by the first moving picture processing unit, which have been transferred from the memory unit prior to the processing start of the intra-frame prediction for the processing of the one macroblock of the second plural macroblocks by the second moving picture processing unit, and   wherein the second moving picture processing unit executes the processing of the one macroblock of the second plural macroblocks using the selected result of processing.   
     
     
         29 . The functional block according to  claim 27 ,
 wherein the first moving picture processing unit and the second moving picture processing unit respectively include memories that store therein data related to the results of processing of macroblocks, and   wherein the first moving picture processing unit and the second moving picture processing unit respectively use the data stored in the memories and related to the results of processing of the macroblocks upon intra-frame prediction for processing of succeeding macroblocks immediately following the macroblocks.   
     
     
         30 . The functional block according  claim 27 ,
 wherein the first moving picture processing unit and the second moving picture processing unit each include a cascade connection of a plurality of input/output interfaces respectively coupled to the plural functional subunits,   wherein the input/output interfaces transfer data related to the results of processing of macroblocks by an associated one of the first moving picture processing unit or the second moving picture processing unit, and the second moving picture processing unit, and   wherein an output of the cascade connection of the input/output interfaces of the first moving picture processing unit is coupled to an input of the cascade connection of the input/output interfaces of the second moving picture processing unit, an output of the cascade connection of the input/output interfaces of the second moving picture processing unit is coupled to an input of the memory unit via a second data path, and an output of the memory unit is coupled to an input of the cascade connection of the input/output interfaces of the first moving picture processing unit via a third data path.   
     
     
         31 . The functional block according to  claim 30 , wherein the input/output interfaces discriminate whether corresponding subunits use the transferred data related to the results of processing of the macroblocks, and supply the data to the corresponding subunits when the subunits use the same. 
     
     
         32 . The functional block according to  claim 27 , further comprising a controller which analyzes a bit stream containing the first plural macroblocks and the second plural macroblocks, and thereby supplies the first plural macroblocks to the first moving picture processing unit, and supplies the second plural macroblocks to the second moving picture processing unit. 
     
     
         33 . The functional block according to  claim 32 , further comprising a direct memory access controller which transfers the bit stream between a storage device and the first and second moving picture processing units. 
     
     
         34 . The functional block according to  claim 27 , wherein the functional subunits of the first moving picture processing unit and the second moving picture processing unit are comprised of common hardware resources usable in the video decoding and the video coding and supplied with an operation mode signal for instructing a system initialization sequence to operate the functional block as either a coding device or a decoding device, and each of the common hardware resources is operated as a device instructed by the operation mode signal in response to the instruction based on the operation mode signal. 
     
     
         35 . The functional block according to  claim 27 , wherein the memory unit includes a line memory that stores therein the data corresponding to at least the one row, related to the results of processing of the first plural macroblocks arranged within the one row of the one picture, by the first moving picture processing unit. 
     
     
         36 . A semiconductor integrated circuit including as a core, a functional block capable of executing at least any one of video coding and video decoding based on H. 264/AVC, comprising:
 at least a first moving picture processing unit and a second moving picture processing unit capable of parallel operations; and   a memory unit which is coupled to the first moving picture processing unit and the second moving picture processing unit and stores therein data related to results of processing by the first moving picture processing unit,   wherein, when the first moving picture processing unit and the second moving picture processing unit perform the parallel operations, a data processing unit processed by each of the first moving picture processing unit and the second moving picture processing unit includes macroblocks having a plurality of sample numbers,   wherein each of the first moving picture processing unit and the second moving picture processing unit includes pipeline connections of a plurality of functional subunits operated with timings different from one another in function and different in pipeline operation so as to execute a selected one of the video coding and the video decoding,   wherein the functional block is operative to process a coded frame picture,   wherein, when the functional block processes the coded frame picture, the first moving picture processing unit processes as data units respective sets of macroblock pairs of same rows in first plural macroblocks arranged within one row of one picture and second plural macroblocks arranged within a first succeeding row located immediately after the one row, and the second moving picture processing unit processes as data units respective sets of macroblock pairs of same rows in third plural macroblocks arranged within a second succeeding row located immediately after the first succeeding row located immediately after the second succeeding row, and the timing to start the pipeline operation of the second moving picture processing unit is delayed by four or more timeslots of the pipeline operation from the timing to start the pipeline operation of the first moving picture processing unit, and   wherein data related to the results of processing of at least the plural adjacent macroblocks of the first moving picture processing unit are transferred from the memory unit to the second moving picture processing unit prior to the start of processing for the inter-frame prediction for the processing of the one macroblock by the second moving picture processing unit.   
     
     
         37 . The semiconductor integrated circuit according to  claim 36 ,
 wherein a result of processing of one macroblock of the plural adjacent macroblocks is selected in accordance with a prediction mode used for the intra-frame prediction of the one macroblock from the data related to the results of processing of the plural adjacent macroblocks by the first moving picture processing unit, which have been transferred from the memory unit prior to the processing start of the intra-frame prediction for the processing of the one macroblock of the second plural macroblocks by the second moving picture processing unit, and   wherein the second moving picture processing unit executes the processing of the one macroblock of the second plural macroblocks using the selected result of processing.   
     
     
         38 . The semiconductor integrated circuit according to  claim 36 ,
 wherein the first moving picture processing unit and the second moving picture processing unit respectively include memories that store therein the data related to the results of processing of macroblocks, and   wherein the first moving picture processing unit and the second moving picture processing unit respectively use the data stored in the memories and related to the results of processing of the macroblocks upon intra-frame prediction for processing of succeeding macroblocks immediately following the macroblocks.   
     
     
         39 . The semiconductor integrated circuit according to  claim 36 ,
 wherein the first moving picture processing unit and the second moving picture processing unit each include a cascade connection of a plurality of input/output interfaces respectively coupled to the plurality of functional subunits,   wherein the input/out interfaces transfer data related to the results of processing of macroblocks by an associated one of the first moving picture processing unit or the second moving picture processing unit, and   wherein an output of the cascade connection of the input/output interfaces of the first moving picture processing unit is coupled to an input of the cascade connection of the input/output interfaces of the second moving picture processing unit, an output of the cascade connection of the input/output interfaces of the second moving picture processing unit is coupled to an input of the memory unit via a second data path, and an output of the memory unit is coupled to an input of the cascade connection of the input/output interfaces of the first moving picture processing unit.   
     
     
         40 . The semiconductor integrated circuit according to  claim 39 , wherein the input/output interfaces discriminate whether corresponding subunits use the transferred data related to the results of processing of the macroblocks, and the data are supplied to the corresponding subunits when the subunits use the same. 
     
     
         41 . The semiconductor integrated circuit according to  claim 36 , further comprising a controller which analyzes a bit stream containing the first plural macroblocks and the second plural macroblocks and thereby supplies the first plural macroblocks to the first moving picture processing unit and supplies the second plural macroblocks to the second moving picture processing unit. 
     
     
         42 . The semiconductor integrated circuit according to  claim 41 , further comprising a direct memory access controller which transfers the bit stream between a storage device and the first and second moving picture processing units. 
     
     
         43 . The semiconductor integrated circuit according to  claim 36 , wherein the functional subunits of the first moving picture processing unit and the second moving picture processing unit are comprised of common hardware resources usable in the video decoding and the video coding and supplied with an operation mode signal for instructing a system initialization sequence to operate the functional block as either a coding device or a decoding device, and each of the common hardware resources is operated as a device instructed by the operation mode signal in response to the instruction based on the operation mode signal. 
     
     
         44 . The semiconductor integrated circuit according to  claim 36 , wherein the memory unit includes a line memory that stores therein the data corresponding to at least the one row, related to the results of processing of the first plural macroblocks arranged within the one row of the one picture, by the first moving picture processing unit.