Integrated circuits to control access to multiple layers of memory in a solid state drive

Abstract

Circuits to control access to memory; for example, third dimension memory are disclosed. An integrated circuit (IC) may be configured to control access to memory cells. For example, the IC may include a memory having memory cells that are vertically disposed in multiple layers of memory. The IC may include a memory access circuit configured to control access to a first subset of the memory cells in response to access control data in a second subset of the memory cells. Each memory cell may include a non-volatile two-terminal memory element that stores data as a plurality of conductivity profiles that can be non-destructively sensed by applying a read voltage across the two terminals of the memory element. New data can be written by applying a write voltage across the two terminals of the memory element. The two-terminal memory elements can be arranged in a two-terminal cross-point array configuration.

1 . A data storage system including non-Flash, re-writeable non-volatile memory, comprising:
 a plurality of semiconductor die, each die including circuitry fabricated in a logic layer of the die, the circuitry of each die configured to implement a solid state drive (SSD) that emulates at least one hard disk drive (HDD);   a plurality of re-writeable non-volatile memories, each re-writeable non-volatile memory arranged in direct contact with and fabricated directly above a corresponding one of the plurality of semiconductor die, each re-writeable non-volatile memory including a plurality of vertically stacked memory layers with each memory layer in direct contact with an adjacent memory layer;   each memory layer positioned in a memory plane that is distinct from memory planes of other memory layers, and each memory layer including at least one re-writeable non-volatile memory array embedded therein and electrically coupled with the corresponding die circuitry,   at least a portion of the circuitry of each die configured to perform data operations on the corresponding memory array; and   a memory access circuit included in the circuitry of each die and configured to enable or disable data operations access to a first subset of the plurality of memory elements in a corresponding re-writeable non-volatile memory in response to access control data;   the access control data stored in an access control memory included in a second subset of the plurality of memory elements, wherein at least one memory element in the first subset of the plurality of memory elements resides in a different memory plane in the re-writeable non-volatile memory than at least another memory element in the access control memory.   
     
     
         2 . The data storage system of  claim 1 , wherein the memory access circuit is further configured to communicate with any of the plurality of vertically stacked memory layers of its respective re-writeable non-volatile memory to determine the access control data for the first subset of the plurality of memory elements. 
     
     
         3 . The data storage system of  claim 1 , wherein the memory access circuit comprises a circuit portion and a memory portion, the circuit portion is positioned in the logic layer of its respective die and the memory portion is positioned in one or more of the plurality of vertically stacked memory layers associated with its respective re-writeable non-volatile memory. 
     
     
         4 . The data storage system of  claim 1 , wherein the plurality of vertically stacked memory layers are configurable to include an amount of the second subset of the plurality of memory elements, the amount being distributed in a vertical arrangement. 
     
     
         5 . The data storage system of  claim 4 , wherein the vertical arrangement comprises a selectable amount of the second subset of the plurality of memory elements without substantially increasing a die area of its respective die.