Method and apparatus for buried-channel semiconductor device

Abstract

Methods and apparatus of integrating a buried-channel PMOS into a BiCMOS process. The apparatus comprises at least one bipolar transistor and at least one MOS device coupled to the at least one bipolar transistor, such that a gate of the at least one MOS device may be coupled to an emitter of the at least one bipolar transistor. The MOS device comprises a buried channel having mobility means, such as strained silicon for promoting hole mobility in the buried channel, and confinement means, such as a cap layer disposed proximate to the buried channel for limiting leakage of holes from the buried channel. The apparatus may be formed by exposing a substrate in a PMOS, forming a SiGe layer on the substrate, forming an oxide layer on the SiGe layer, masking the PMOS, and removing at least some of the oxide and at least some of the SiGe layer.

1 . A method of integrating a buried-channel PMOS into a BiCMOS process, the method comprising:
 exposing a substrate in a PMOS;   forming a SiGe layer on the substrate;   forming an oxide layer on the SiGe layer;   masking the PMOS; and   removing at least some of the oxide and at least some of the SiGe layer.   
     
     
         2 . The method of  claim 1 , wherein the oxide layer is formed using a PECVD process. 
     
     
         3 . An apparatus, comprising:
 at least one bipolar transistor;   at least one MOS device, the MOS device comprising a gate coupled to an emitter of the at least one bipolar transistor, the MOS device comprising:   mobility means for promoting hole mobility in a buried channel; and   confinement means for limiting leakage of holes from the buried channel.   
     
     
         4 . The apparatus of  claim 3 , wherein the mobility means comprises straining a material in the buried channel. 
     
     
         5 . The apparatus of  claim 3 , wherein the mobility means comprises 20-30% germanium in the buried channel. 
     
     
         6 . The apparatus of  claim 3 , wherein the confinement means comprises increasing a threshold voltage (V hc ) of a material in the buried channel. 
     
     
         7 . The apparatus of  claim 3 , wherein the confinement means comprises forming a thin cap layer proximate to the buried channel. 
     
     
         8 . The apparatus of  claim 7 , wherein the thin cap layer is formed above the buried channel. 
     
     
         9 . The apparatus of  claim 7 , wherein the cap layer comprises silicon. 
     
     
         10 . The apparatus of  claim 7 , wherein the cap layer is doped with a p-type material. 
     
     
         11 . The apparatus of  claim 10 , wherein V hc  is increased by increasing the density of doping in the cap layer.