Solid-state image sensing apparatus

Abstract

In a solid-state image sensing apparatus of an addressing method, a clock-conversion part generates a high-speed clock signal having a frequency two times or more the frequency of a low-speed clock signal. A signal processing part receives 10-bit pixel data through a horizontal signal line, performs predetermined signal processing, and passes parallel-format data to a switching part. The switching part selects each one bit of the parallel-format 10-bit data in a predetermined sequence to output from an output terminal using the high-speed clock signal from the clock-conversion part as a switching command, thus converts the parallel-format data into serial-format data, and passes it to an output buffer. The output buffer externally outputs differential output of normal video data and inverted video data individually from output terminals. Accordingly, the problems in power consumption, noises, and unnecessary radiation are solved, and higher-speed output is achieved.

1 . A solid-state image sensing device comprising:
 a pixel area which has an electric-charge generation part for generating signal electric charge, and outputs an analog pixel signal corresponding to the signal electric charge generated by the electric-charge generation part;   an AD-conversion part which converts the pixel signal output from the pixel area into pixel data, which is digital data;   a high-speed clock generation part which generates a high-speed clock signal, which is a pulse signal having a higher frequency than a basic clock signal that is a basic pulse signal corresponding to a driving pulse signal for driving the pixel area; and   a data-output part which externally outputs a predetermined output data based on the pixel data that is converted into digital data by the AD-conversion part in accordance with the high-speed clock signal generated by the high-speed clock generation part.   
     
     
         2 . The solid-state image sensing device according to  claim 1 ,
 wherein the data-output part outputs the output data in accordance with both a rising edge and a falling edge of the high-speed clock signal generated by the high-speed clock generation part.   
     
     
         3 . The solid-state image sensing device according to  claim 1 ,
 wherein the high-speed clock generation part generates the high-speed clock signal having a frequency of k times (k is a positive integer of 2 or more) or more the frequency of the basic clock signal.   
     
     
         4 . The solid-state image sensing device according to  claim 1 ,
 wherein the high-speed clock generation part generates the high-speed clock signal having a frequency of k times (k is a positive integer of 2 or more) or more the frequency of the basic clock signal and in synchronism with the basic clock signal.   
     
     
         5 . The solid-state image sensing device according to  claim 1 ,
 wherein the high-speed clock generation part and the data-output part are disposed on the semiconductor substrate of the solid-state image sensing device in a state in which a partitioning area of both of the parts is substantially complicated.   
     
     
         6 . The solid-state image sensing device according to  claim 1 ,
 wherein the high-speed clock generation part and the data-output part are disposed on the semiconductor substrate of the solid-state image sensing device with being adjacent to each other at an edge of a partitioning area of both of the parts.   
     
     
         7 . The solid-state image sensing device according to  claim 1 ,
 wherein the data-output part comprises:   a data receiving part which receives, in synchronism with the basic clock signal, the pixel data in a parallel format, which has been converted into digital data by the AD-conversion part; and   a data processing part which performs a predetermined processing on the parallel-format pixel data received by the data receiving part using the high-speed clock signal generated by the high-speed clock generation part to output data having a higher frequency than the clock frequency of the parallel-format pixel data.   
     
     
         8 . The solid-state image sensing device according to  claim 7 ,
 wherein the high-speed clock generation part generates a plurality of the high-speed clock signals having individually different frequencies, and   the data processing part comprises: a first data processing part which performs a predetermined digital signal processing on the parallel-format pixel data received by the data receiving part using the high-speed clock signal having a lower frequency among the plurality of high-speed clock signals in order to output the data in a parallel format; and a second data processing part which performs predetermined processing on the parallel-format data output from the signal processing part using the high-speed clock signal having a higher frequency among the plurality of high-speed clock signals in order to output the data having a higher frequency than the clock frequency of the parallel-format data.   
     
     
         9 . The solid-state image sensing device according to  claim 1 ,
 further comprising a communication part for communicating with an external controller,   wherein the high-speed clock generation part switches the high-speed clock frequencies based on a frequency switching instruction received by the communication part.   
     
     
         10 . The solid-state image sensing device according to  claim 1 ,
 wherein the data-output part comprises a high-speed clock output part which outputs the high-speed clock signal generated by the high-speed clock generation part from the terminal other than the terminal for outputting the output data.   
     
     
         11 . The solid-state image sensing device according to  claim 7 ,
 wherein the data processing part comprises a parallel-serial conversion part which converts the parallel-format pixel data received by the data receiving part into serial-format data using the high-speed clock signal generated by the high-speed clock generation part.   
     
     
         12 . The solid-state image sensing device according to  claim 11 ,
 wherein the parallel-serial conversion part has a switching part which includes an output terminal for outputting by selecting any one of a plurality of input terminals receiving individual input of the parallel-format data and each data input into the terminal, and a control terminal for receiving input of the high-speed clock signal generated by the high-speed clock generation part as a switching command,   wherein any one of each data input into the input terminal is selected and output from the output terminal to be converted into the serial format data in accordance with a predetermined procedure using the high-speed clock signal generated by the high-speed clock generation part as the switching command.   
     
     
         13 . The solid-state image sensing device according to  claim 7 ,
 wherein the data processing part comprises a parallel-serial conversion part which converts the parallel-format pixel data of the plurality of pixels received by the data receiving part using the high-speed clock signal generated by the high-speed clock generation part for each bit of the parallel-format data in order to convert the plurality of pixel data into serial format data.   
     
     
         14 . The solid-state image sensing device according to  claim 7 ,
 wherein the high-speed clock generation part generates a plurality of the high-speed clock signals having individually different frequencies, and   the data processing part comprises a first parallel-serial conversion part which performs conversion of the parallel-format pixel data on a plurality of pixels received by the data receiving part into serial-format data for the plurality of pixels for each bit of the parallel-format data using the high-speed clock signal having a lower frequency among the plurality of high-speed clock signals generated by the high-speed clock generation part, and a second parallel-serial conversion part which performs conversion of the serial-format data for each bit output from the first parallel-serial conversion part into serial-format data for the bits using the high-speed clock signal having a higher frequency among the plurality of high-speed clock signals generated by the high-speed clock generation part.   
     
     
         15 . The solid-state image sensing device according to  claim 7 ,
 wherein the high-speed clock generation part generates a plurality of the high-speed clock signals having individually different frequencies, and   the data processing part comprises: a first parallel-serial conversion part which performs conversion of the parallel-format pixel data on a plurality of pixels received by the data receiving part into serial-format data for the bits for each pixel using the high-speed clock signal having a lower frequency among the plurality of high-speed clock signals generated by the high-speed clock generation part; and a second parallel-serial conversion part which performs conversion of the serial-format data for each of the pixels output from the first parallel-serial conversion part into serial-format data for the plurality of pixels using the high-speed clock signal having a higher frequency among the plurality of high-speed clock signals generated by the high-speed clock generation part.   
     
     
         16 . The solid-state image sensing device according to  claim 1 ,
 wherein the data-output part generates a high-speed clock signal having a sufficiently high frequency so as to output the pixel data and additional data together, which is the other information on the pixel data, and   the data-output part processes and outputs the parallel-format pixel data received by the data receiving part and the additional data based on a predetermined rule using the high-speed clock signal generated by the high-speed clock generation part.   
     
     
         17 . The solid-state image sensing device according to  claim 13 ,
 wherein the data-output part comprises a parallel-serial conversion part which converts the parallel-format pixel data received by the data receiving part and the additional data using the high-speed clock signal generated by the high-speed clock generation part.   
     
     
         18 . The solid-state image sensing device according to  claim 17 ,
 wherein the pixel area has a plurality of the electric charge generation parts in a matrix, and outputs the pixel signal for each column for each row, and   the additional data is data indicating a change of the row.   
     
     
         19 . The solid-state image sensing device according to  claim 17 ,
 wherein the pixel area has a plurality of the electric charge generation parts in a matrix, and outputs the pixel signal for each column for each row, and   the additional data is data indicating a change of a frame image, which is one piece of an image corresponding to the pixel area in which the electric charge generation parts are disposed in a matrix.   
     
     
         20 . The solid-state image sensing device according to  claim 11 ,
 wherein the data-output part has one data-output terminal for externally outputting n-bit output data, expressed in the serial format, generated by the parallel-serial conversion part.   
     
     
         21 . The solid-state image sensing device according to  claim 11 ,
 wherein the data-output part has a strobe-data generation part for generating strobe data which can reproduce the clock signal by performing an exclusive-OR operation with n-bit output data, expressed in the serial format, generated by the parallel-serial conversion part, and   the strobe-data generation part has a strobe-output terminal for externally outputting the strobe data in addition to the data-output terminal.   
     
     
         22 . The solid-state image sensing device according to  claim 13 ,
 wherein the data-output part has n data-output terminals for externally outputting the serial-format data generated by the parallel-serial conversion part for the plurality of pixels as n-bit data, expressed in the parallel format for each pixel.   
     
     
         23 . The solid-state image sensing device according to  claim 11 ,
 wherein the data-output part has a differential conversion part which converts the pixel data into differential-format data including normal data having the same polarity as n-bit output data, expressed in the serial format, generated by the parallel-serial conversion part and inverted data having the opposite polarity, and   the differential conversion part has two data-output terminals for externally outputting the normal data and the inverted data individually.   
     
     
         24 . The solid-state image sensing device according to  claim 23 ,
 wherein the data-output part has a high-speed clock output part which converts the pixel data into differential-format clock signal including a normal high-speed clock signal having the same polarity as the high-speed clock signal generated by the high-speed clock generation part and an inverted high-speed clock signal having the opposite polarity, and   the high-speed clock output part has two clock-output terminals for externally outputting the normal high-speed clock signal and the inverted high-speed clock signal individually in addition to the two data-output terminals.   
     
     
         25 . The solid-state image sensing device according to  claim 23 ,
 wherein the data-output part has a strobe-data generation part for generating strobe data which can reproduce the clock signals by performing exclusive-OR operations between the corresponding data with the normal data and the inverted data generated by the differential conversion part, respectively, and   the strobe-data generation part has strobe-output terminals for externally outputting the corresponding strobe data for each of the normal data and the inverted data in addition to the two data-output terminals.   
     
     
         26 . The solid-state image sensing device according to  claim 1 ,
 wherein the data-output part has a differential conversion part for the n bits, which converts the pixel data into differential-format data including normal data having the same polarity as n-bit data received, expressed in the parallel format, and inverted data having the opposite polarity, and   each of the differential conversion parts for the n bits has two data-output terminals for externally outputting the normal data and the inverted data individually.   
     
     
         27 . The solid-state image sensing device according to  claim 26 ,
 wherein the data-output part has a high-speed clock output part which converts the clock signal into a differential-format clock signal including a normal high-speed clock signal having the same polarity as the high-speed clock signal generated by the high-speed clock generation part and an inverted high-speed clock signal having the opposite polarity, and   the high-speed clock output part has two clock-output terminals for externally outputting the normal high-speed clock signal and the inverted high-speed clock signal individually in addition to the two data-output terminals individually disposed for the n bits.   
     
     
         28 . The solid-state image sensing device according to  claim 1 , further comprising:
 an optical system for leading incident light into the pixel area; and   a digital signal processor for performing the output-data processing.   
     
     
         29 . A solid-state image sensing device comprising:
 a pixel area which includes an electric-charge generation part for generating electric charge in accordance with incident light; and   an AD-conversion part which converts an analog signal sent from the pixel area into a digital signal,   wherein the pixel area is driven in accordance with a first clock signal, and   the digital signal from the AD-conversion part is output in accordance with a second clock signal having a higher frequency than that of the first clock signal.   
     
     
         30 . A camera comprising:
 a pixel area which includes an electric-charge generation part for generating electric charge in accordance with incident light;   an AD-conversion part which converts an analog signal sent from the pixel area into a digital signal; and   an optical system for leading incident light into the pixel area,   wherein the pixel area is driven in accordance with a first clock signal, and   the digital signal from the AD-conversion part is output in accordance with a second clock signal having a higher frequency than that of the first clock signal.