Processor for executing highly efficient vliw

Abstract

A 32-bit instruction 50 is composed of a 4-bit format field 51 , a 4-bit operation field 52 , and two 12-bit operation fields 59 and 60 . The 4-bit operation field 52 can only include (1) an operation code “cc” that indicates a branch operation which uses a stored value of the implicitly indicated constant register 36 as the branch address, or (2) a constant “const”. The content of the 4-bit operation field 52 is specified by a format code provided in the format field 51.

1 - 29 . (canceled) 
     
     
         30 . A processing method in a microprocessor, comprising:
 fetching an instruction including a plurality of operation fields; and   decoding the plurality of operation fields in the fetched instruction in parallel with each other;   wherein the plurality of operation fields are categorized into two types, a first type of operation field and a second type of operation field,   the plurality of operation fields includes one operation field of the first type and at least two operation fields of the second type,   the first type of operation field is composed of a condition code with no operand thereof,   the second type of operation field is composed of an operation code and one or more operands, and   wherein the condition code in the first type of operation field controls an execution flow of the instruction which includes the at least two operation fields of the second type.   
     
     
         31 . The processing method of  claim 30 , wherein the condition code in the first type of operation field is a conditional operation code. 
     
     
         32 . The processing method of  claim 30 , wherein a bit length of at least one of the plurality of operation fields is different than a bit length of another one of the plurality of operation fields. 
     
     
         33 . The processing method of  claim 30 , wherein the operation field of the first type and the at least two operation fields of the second type are allocated in a predetermined order in the instruction. 
     
     
         34 . The processing method of  claim 30 , wherein a bit length of the first type of operation field is shorter than a bit length of the second type of operation field. 
     
     
         35 . The processing method of  claim 34 , wherein the instruction is a 32-bit instruction and the plurality of operation fields is three operation fields. 
     
     
         36 . A microprocessor comprising:
 a fetch unit that fetches an operation code from a external memory,   an instruction register that holds the fetched operation code,   a decoder unit that decodes the operation code held in the instruction register, and   an operation unit that executes a plurality of the decoded operation codes in parallel,   wherein the fetch unit fetches a first operation code, a second operation code and third operation code in a single fetch, and fetches a fourth operation code in a subsequent single fetch, the fourth operation code being different from any one of the first operation code, the second operation code and the third operation code,   wherein the operation unit executes the first operation code and the second operation code in parallel, and subsequently executes the third operation code and the fourth operation code in parallel.   
     
     
         37 . A method of executing parallel operations in a microprocessor, said method comprising:
 fetching a first operation code, a second operation code and a third operation code in a single fetch,   fetching a fourth operation code in a subsequent single fetch, the fourth operation code being different from any one of the first operation code, the second operation code and the third operation code,   executing the first operation code and the second operation code in parallel, and subsequently executing the third operation code and the fourth operation code in parallel.   
     
     
         38 . A VLIW processor, comprising:
 fetch means for fetching an instruction that includes a plurality of operation fields;   a decoder unit for decoding the plurality of operation fields in the fetched instruction in parallel with each other; and   a program counter for holding an address of the instruction;   the VLIW processor being characterized in that:   the plurality of operation fields are categorized into two types, a first type of operation field and a second type of operation field,   the plurality of operation fields include one operation field of the first type and at least one operation field of the second type,   the first type of operation field is composed of a control code with no operand thereof,   the second type of operation field is composed of an operation code and one or more operands, and   wherein the control code in the first type of operation field controls the program counter so that a control flow of a program is achieved.   
     
     
         39 . The VLIW processor of  claim 38 , wherein the decoder unit includes:
 a first decoder for decoding the control code in the operation field of the first type, and   at least one second decoder for decoding the operation code in each of the at least one operation field of the second type.   
     
     
         40 . The VLIW processor of  claim 39 , wherein the program counter updates its holding value in accordance with a decoded result of the first decoder. 
     
     
         41 . The VLIW processor of  claim 38 , wherein the control code in the first type of operation field is related to a branch operation. 
     
     
         42 . The VLIW processor of  claim 38 , wherein a bit length of at least one of the plurality of operation fields is different than a bit length of another one of the plurality of operation fields. 
     
     
         43 . The VLIW processor of  claim 38 , wherein the first type of operation field and the second type of operation field are each allocated in a predetermined order in an instruction. 
     
     
         44 . The VLIW processor of  claim 38 , further comprising a format decoder for decoding a format field in the fetched instruction. 
     
     
         45 . The VLIW processor of  claim 38 , wherein a bit length of the first type of operation field is shorter than a bit length of the second type of operation field. 
     
     
         46 . The VLIW processor of  claim 45 , wherein a bit length of the instruction is 32-bit or more. 
     
     
         47 . The VLIW processor of  claim 38 , wherein the instruction is a L-bit instruction and the plurality of operation fields is M operation fields, and wherein said decoder unit comprises M decoder units, each of which includes a dedicated decoder unit that decodes one of the M operation fields in the fetched instruction that is associated one-to-one therewith, said VLIW processor further comprising:
 M operation units each of which executes an operation indicated in the associated operation field in parallel with each other.   
     
     
         48 . The VLIW processor of  claim 47 , wherein a bit length of at least one of the M operation fields is different than a bit length of another one of the M operation fields. 
     
     
         49 . The VLIW processor of  claim 47 , wherein M is 2 or more. 
     
     
         50 . The VLIW processor of  claim 49 , wherein L is 32 or more.