Duty cycle corrector circuits

Abstract

Duty cycle corrector circuits that utilize differing unit delay elements in their delay lines in either a graduated or a stepped unit time delay arrangement are for synchronizing with a clock signal. These graduated or a stepped unit time delays allow reduction in the number of the fine unit delay elements of the delay lines by placing a fine delay element granularity at the most critical timings to sense and adjust for the portion of the clock signal time period that are high speed or critical.

1 . A duty cycle corrector (DCC) circuit, comprising:
 a plurality of delay lines, wherein each delay line contains a plurality of serially-connected delay elements that differ in unit time delay and wherein the plurality of delay lines are sequentially coupled input to output;   an input buffer coupled to a first delay line; and   a phase detector coupled to a final delay line and the input buffer, wherein the phase detector is configured to compare an input clock signal received by the input buffer and compare it to a delayed clock signal coupled from the final delay line and adjust the plurality of delay lines to synchronize the input clock signal and the delayed clock signal.   
     
     
         2 . The duty cycle corrector (DCC) circuit of  claim 1 , wherein the plurality of delay lines are selected from the group consisting of stepped delay lines, having a stepped profile in the unit time delay of the serially-connected delay elements of each delay line, and graduated delay lines, having a graduated profile in the unit time delay of the serially-connected delay elements of each delay line. 
     
     
         3 . The duty cycle corrector (DCC) circuit of  claim 2 , wherein the stepping or graduating of the profile of unit time delay of the serially-connected delay elements is selected according to a resolution de-rating table or a curve specified to achieve acceptable resolution at specified operating frequency ranges. 
     
     
         4 . The duty cycle corrector (DCC) circuit of  claim 2 , wherein the stepped or graduated profile of the unit time delay of the serially-connected delay elements has multiple peaks and valleys in the profile, where the unit time delay of the serially-connected delay elements are stepped or graduated up and/or down into. 
     
     
         5 . The duty cycle corrector (DCC) circuit of  claim 1 , wherein the phase detector configured to adjust the plurality of delay lines comprises the phase detector configured to select a number of the plurality of serially-connected delay elements of each of the delay lines to be the same number. 
     
     
         6 . The duty cycle corrector (DCC) circuit of  claim 1 , wherein each of the plurality of delay lines has a length, and wherein the length of each of the plurality of delay lines is the same. 
     
     
         7 . The duty cycle corrector (DCC) circuit of  claim 1 , wherein an output of one of the plurality of delay lines is configured to be 180° out of phase with another one of the plurality of delay lines. 
     
     
         8 . A duty cycle corrector (DCC) circuit, comprising:
 a plurality of delay lines, wherein each delay line contains a plurality of serially-connected delay elements, wherein each delay line utilizes time delays with a graduated time delay arrangement, and wherein the plurality of delay lines are sequentially coupled input to output;   a phase detector coupled to a final delay line and an input clock signal, wherein the phase detector is configured to compare the input clock signal and compare it to a delayed clock signal coupled from the final delay line and adjust the plurality of delay lines to synchronize the input clock signal and the delayed clock signal.   
     
     
         9 . The duty cycle corrector (DCC) circuit of  claim 8 , wherein each delay line utilizes time delays with multiple graduated time delay arrangements, producing at least one valley in a unit delay profile of each delay line. 
     
     
         10 . The duty cycle corrector (DCC) circuit of  claim 8 , wherein the delayed clock signal coupled from the final delay line is configured to be phase shifted 360° from the input clock signal. 
     
     
         11 . The duty cycle corrector (DCC) circuit of  claim 8 , wherein each of the plurality of delay lines has a length. 
     
     
         12 . The duty cycle corrector (DCC) circuit of  claim 8 , wherein the length of each of the plurality of delay lines is the same. 
     
     
         13 . The duty cycle corrector (DCC) circuit of  claim 8 , wherein the length of one of the plurality of delay lines is different than the length of another one of the plurality of delay lines. 
     
     
         14 . A duty cycle corrector (DCC) circuit, comprising:
 a plurality of delay lines, wherein each delay line contains a plurality of serially-connected delay elements, wherein each delay line utilizes time delays with a stepped time delay arrangement, and wherein the plurality of delay lines are sequentially coupled input to output;   a phase detector coupled to a final delay line and an input clock signal, wherein the phase detector is configured to compare the input clock signal and compare it to a delayed clock signal coupled from the final delay line and adjust the plurality of delay lines to synchronize the input clock signal and the delayed clock signal.   
     
     
         15 . The duty cycle corrector (DCC) circuit of  claim 14 , wherein each delay line utilizes time delays with multiple stepped time delay arrangements, producing at least one valley in a unit delay profile of each delay line. 
     
     
         16 . The duty cycle corrector (DCC) circuit of  claim 14 , wherein the delayed clock signal coupled from the final delay line is configured to be phase shifted 360° from the input clock signal. 
     
     
         17 . The duty cycle corrector (DCC) circuit of  claim 14 , wherein the phase detector configured to adjust the plurality of delay lines comprises the phase detector configured to select a number of the plurality of serially-connected delay elements of each of the delay lines to be the same number. 
     
     
         18 . The duty cycle corrector (DCC) circuit of  claim 14 , wherein the plurality of delay lines comprises two delay lines, wherein an input of a second delay line of the two delay lines is coupled to the output of a first delay line of the two delay lines, wherein an input of the first delay line is coupled to receive the input clock signal, and wherein the second delay line is the final delay line. 
     
     
         19 . The duty cycle corrector (DCC) circuit of  claim 18 , wherein the first delay line and the second delay line each have a length. 
     
     
         20 . The duty cycle corrector (DCC) circuit of  claim 19 , wherein a phase of a delayed clock signal coupled from the first delay line is dependent on the relative lengths of the first and second delay lines to each other. 
     
     
         21 . The duty cycle corrector (DCC) circuit of  claim 18 , wherein a phase of a delayed clock signal coupled from the first delay line is shifted 180° from a phase of the delayed clock signal coupled from the final delay line.