Semiconductor integrated circuit device

Abstract

Disclosed is a semiconductor integrated circuit device that includes a ring oscillator circuit, performs a proper oscillation operation, and expands the range of oscillation frequency variation. The ring oscillator circuit includes, for instance, plural differential amplifier circuits. MOS transistors are respectively added to input nodes of a differential pair of the differential amplifier circuits. Further, gate control circuits are incorporated to control the gates of the MOS transistors, respectively. The gate control circuits cause the MOS transistors to function as an amplitude limiter circuit in mode 3 , exercise control to turn off the amplitude limiter circuit in mode 2 , and use the amplitude limiter circuit to start oscillation in mode 1.

1 . A semiconductor integrated circuit device comprising:
 a ring oscillator circuit that includes a plurality of cascaded differential amplifier circuits,   a control circuit which changes an operation mode of the plurality of cascaded differential amplifier circuits;   wherein the differential amplifier circuits each include:   a first transistor that operates in accordance with a potential difference between a first supply voltage node and a second supply voltage node, serves as one of a pair of differential input transistors, and is configured by coupling the gate thereof to a positive differential input node,   a second transistor that serves as the remaining one of the pair of differential input transistors and is configured by coupling the gate thereof to a negative differential input node,   a first limit transistor that uses a path between the first supply voltage node and the positive differential input node as a source-drain path,   a second limit transistor that uses a path between the first supply voltage node and the negative differential input node as a source-drain path,   a first gate control circuit that controls the gate of the first limit transistor, and   a second gate control circuit that controls the gate of the second limit transistor; and   wherein the first gate control circuit and the second gate control circuit have the operation mode including a first operation mode (mode  3 ), a second operation mode (mode  2 ), and a third operation mode (mode  1 ),   wherein during the first operation mode, the first gate control circuit causes the first limit transistor to function as a first diode for limiting the signal amplitude of the positive differential input node to a threshold voltage thereof, and the second gate control circuit causes the second limit transistor to function as a second diode for limiting the signal amplitude of the negative differential input node to a threshold voltage thereof.   wherein during the second operation mode, the first gate control circuit causes the first limit transistor to function as a first control switch and causes the first control switch to alternate between a conduction state and a nonconduction state, and the second gate control circuit causes the second limit transistor to function as a second control switch and causes the second control switch to remain in either the conduction state or the nonconduction state,   wherein during the third operation mode, the first gate control circuit causes the first control switch to remain in the nonconduction state, and the second gate control circuit causes the second control switch to remain in the nonconduction state.   
     
     
         2 . The semiconductor integrated circuit device according to  claim 1 ,
 wherein the operation mode is changed in accordance with an external register set up.   
     
     
         3 . The semiconductor integrated circuit device according to  claim 1 , further comprising an oscillation confirmation circuit,
 wherein the oscillation confirmation circuit confirms whether oscillation is taking place or not, and when the oscillation confirmation circuit confirm that oscillation is not taking place, the operation mode is changed to the third operation.   
     
     
         4 . The semiconductor integrated circuit device according to  claim 3 ,
 wherein the oscillation confirmation circuit, further comprising a counter circuit,   wherein the counter circuit performs a counting operation in accordance with an output clock signal from the ring oscillator circuit, and when counted value is not smaller than a predetermined value, the counter circuit concludes that oscillation is taking place,   wherein when oscillation is taking place, the operation mode becomes the first operation mode.   
     
     
         5 . The semiconductor integrated circuit device according to  claim 3 ,
 wherein the operation mode is changed between the second operation mode  2  and the third operation mode in accordance with a result of the oscillation confirmation circuit.   
     
     
         6 . The semiconductor integrated circuit device according to  claim 1 , wherein the first transistor, the second transistor, the first limit transistor, and the second limit transistor are of the same conductivity type. 
     
     
         7 . The semiconductor integrated circuit device according to  claim 1 , wherein the first gate control circuit includes a first switch, which is coupled between the gate of the first limit transistor and the positive differential input node, a second switch, which is coupled between the gate of the first limit transistor and the second supply voltage node, and a third switch, which is coupled between the gate of the first limit transistor and the first supply voltage node; and wherein the second gate control circuit includes a fourth switch, which is coupled between the gate of the second limit transistor and the negative differential input node, and a fifth switch, which is coupled between the gate of the second limit transistor and the first supply voltage node. 
     
     
         8 . The semiconductor integrated circuit device according to  claim 7 , wherein each of the differential amplifier circuits further includes a first current source, which is coupled between the second supply voltage node and the drain of the first transistor to output a current in accordance with an oscillation frequency setting for the ring oscillator circuit; a second current source, which is coupled between the second supply voltage node and the drain of the second transistor to output a current in accordance with the oscillation frequency setting; a first inverter circuit, which performs an inversion operation by using the drain of the first transistor as an input and the drain of the second transistor as an output; and a second inverter circuit, which performs an inversion operation by using the drain of the second transistor as an input and the drain of the first transistor as an output. 
     
     
         9 . A semiconductor integrated circuit device comprising:
 a ring oscillator circuit that includes a plurality of cascaded differential amplifier circuits,   a control circuit which changes an operation mode of the plurality of cascaded differential amplifier circuits;   wherein the operation mode include a first operation mode for a first frequency, a second operation mode for a second frequency, and a third operation mode for stopping the oscillation,   wherein the operation mode is changed in accordance with an external register set up.   
     
     
         10 . The semiconductor integrated circuit device according to  claim 9 , further comprising an oscillation confirmation circuit,
 wherein the oscillation confirmation circuit confirms whether oscillation is taking place or not, and when the oscillation confirmation circuit confirm that oscillation is not taking place, the operation mode is changed to the third operation.   
     
     
         11 . The semiconductor integrated circuit device according to  claim 9 ,
 wherein the oscillation confirmation circuit, further comprising a counter circuit,   wherein the counter circuit performs a counting operation in accordance with an output clock signal from the ring oscillator circuit, and when counted value is not smaller than a predetermined value, the counter circuit concludes that oscillation is taking place,   wherein when oscillation is taking place, the operation mode becomes the first operation mode.   
     
     
         12 . The semiconductor integrated circuit device according to  claim 9 ,
 wherein the operation mode is changed between the second operation mode  2  and the third operation mode in accordance with a result of the oscillation confirmation circuit.