Power-on reset circuit

Abstract

A power on reset circuit is capable of changing logic level of reset signal at different threshold voltages.

1 . A power-on reset circuit, comprising:
 a first pull-up component, coupled between a power supply and a first node;   a second pull-up component, coupled between the power supply and a second node;   a first pull-down component, coupled to the first node and a common node; and   a first logic component, coupled between the first node and the second node,   wherein the second pull-up component is actuated based on a voltage at the second node.   
     
     
         2 . The power-on reset circuit of  claim 1 , wherein the first pull-up component includes a P-MOSFET, which has a source connected to the power supply, a drain connected to the first node, and a gate connected to the common node, wherein the first pull-down includes an N-MOSFET, which has a source connected to the common node, a drain connected to the first node, and a gate connected to the power supply. 
     
     
         3 . The power-on reset circuit of  claim 1 , wherein the second pull-up component includes a P-MOSFET or a voltage control component. 
     
     
         4 . The power-on reset circuit of  claim 2 , wherein the P-MOSFET has a source connected to the power supply, a drain connected to the first node, and a gate connected to the second node. 
     
     
         5 . The power-on reset circuit of  claim 1 , further comprising a capacitor coupled between the first node and the common node. 
     
     
         6 . A power-on reset circuit, comprising:
 a first pull-up component, coupled between a power supply and a first node;   a first pull-down component, coupled between the first node and the common node;   a second pull-down component, coupled between the common node and a third node;   a first logic component, coupled between the first node and the second node; and   a second logic component, coupled between the second node and the third node,   wherein the second pull-down component is actuated based on a voltage at the third node.   
     
     
         7 . The power-on reset circuit of  claim 6 , wherein the first pull-up component includes a P-MOSFET, which has a source connected to the power supply, a drain connected to the first node, and a gate connected to the common node, wherein the first pull-down includes an N-MOSFET, which has a source connected to the common node, a drain connected to the first node, and a gate connected to the power supply. 
     
     
         8 . The power-on reset circuit of  claim 6 , wherein the second pull-up component includes an N-MOSFET or a voltage control component. 
     
     
         9 . The power-on reset circuit of  claim 8 , wherein the N-MOSFET has a source connected to the common node, a drain connected to the first node, and a gate connected to the third node. 
     
     
         10 . The power-on reset circuit of  claim 6 , further comprising a capacitor coupled between the first node and the common node.