Method and system for enabling real-time speckle processing using hardware platforms

Abstract

An accelerator for the speckle atmospheric compensation algorithm may enable real-time speckle processing of video feeds that may enable the speckle algorithm to be applied in numerous real-time applications. The accelerator may be implemented in various forms, including hardware, software, and/or machine-readable media.

1 . A method for fast computation of a Speckle Algorithm, comprising:
 initializing and setting up a plurality of memory locations;   setting a frame counter is set to 0;   inputting a present frame of a time sequenced image;   computing a bispectrum of the present frame;   adding the present bispectrum computation to previously accumulated bispectrum computations and storing in one of the plurality of memory locations;   incrementing the frame counter;   checking whether the frame counter equals the number of frames to be processed;   incrementing the frame counter when the frame counter is less than the number of frames to be processed and returning to the step of inputting the present frame;   setting the frame counter to zero when the frame counter is equal to the number of frames to be processed and computing the normalization of the accumulated bispectrum computations;   computing an inverse bispectrum computation;   outputting the inverse bispectrum and returning to the step of inputting the present frame.   
     
     
         2 . (canceled) 
     
     
         3 . A system for real-time computation of a method for a Speckle algorithm, as recited in  claim 1 , further comprising:
 a host computer;   a PCI bridge;   an oscillator;   a transmitter synthesizer;   a serializer;   a receiver; and   a FPGA.   
     
     
         4 . The system of  claim 3 , further comprising:
 input and output shielded connectors configured to input and output video data;   an equalizer and cable driver connector to the input and output shielded connectors, respectively; and   the deserializer and serializer are connected to the outputs the equalizer and cable driver, respectively.   
     
     
         5 . The system of  claim 4 , wherein the FPGA further comprises:
 a framing receiver and framing transmitter connected to the outputs form the deserializer and serializer, respectively; and   a decoder and encoder connected to the outputs from the framing receiver and framing transmitter, respectively, and   an SDRAM and the PCI Bridge are connected to the FPGA,   wherein the deserializer is connected to the framing receiver and the serialize is connected to the framing transmitter.   
     
     
         6 . The system of  claim 5 , wherein the FPGA comprises a Speckle engine and the Speckle engine further comprises:
 a startup function and parameter register file configured to control system operation;   an extract tile function connected to a Demean function and configured to provide inputs to an Apodization window;   a first two-dimensional (2-D) Real-Complex FFT connected to the outputs of the Apodization window;   an Intensity function connected to the 2-D Real-Complex FFT;   a Compute Bispectrum function connected to outputs of the Intensity function;   an Averaging Unit connected to outputs of the Compute Bispectrum function;   an inverse two-dimensional (2-D) Real-Complex FFT connected to outputs of the Averaging Unit; and   an Apodization Gain unit connected to outputs of the second two-dimensional (2-D) Real-Complex FFT,   wherein the startup function is connected to the parameter register file, and the Speckle engine, the PCI bridge is connected to the startup function and the SDRAM is connected to the Speckle engine.   
     
     
         7 . The system of  claim 6 , wherein the 2D-FFT is configured to process real-number inputs in a range of at least 0 to 1, inclusive. 
     
     
         8 . The system of  claim 6 , wherein the FFT sizes are at least 64.times.64, 256.times.256, 512.times.512 and 1024.times.1024. 
     
     
         9 . The system of  claim 6 , wherein the inverse FFT sizes are at least 64.times.64, 256.times.256, 512.times.512 and 1024.times.1024 and the range is constrained at the output. 
     
     
         10 .- 16 . (canceled) 
     
     
         17 . A machine-readable medium containing executable instructions that, when executed by a machine, cause the machine to implement a method for fast computation of a Speckle Algorithm, comprising:
 initializing and setting up a plurality of memory locations;   setting a frame counter is set to 0;   inputting a present frame of a time sequenced image;   computing a bispectrum of the present frame;   adding the present bispectrum computation to previously accumulated bispectrum computations and storing in one of the plurality of memory locations;   incrementing the frame counter;   checking whether the frame counter equals the number of frames to be processed;   incrementing the frame counter when the frame counter is less than the number of frames to be processed and returning to the step of inputting the present frame;   setting the frame counter to zero when the frame counter is equal to the number of frames to be processed and computing the normalization of the accumulated bispectrum computations;   computing an inverse bispectrum computation;   outputting the inverse bispectrum and returning to the step of inputting the present frame.   
     
     
         18 . (canceled)