Apparatus for Memory Interface Configuration and Associated Methods

Abstract

An apparatus includes a memory circuit and an interface circuit. The interface circuit is coupled to the memory circuit. The interface circuit selects a phase value of clock signal adapted to clock the memory circuit.

1 - 20 . (canceled) 
     
     
         21 . A method of operating a memory, comprising clocking the memory using a clock signal having a phase value; and changing the phase value of the clock signal adapted to clock the memory circuit during a data capture operation such that the results of the data capture operation meet a specified criterion. 
     
     
         22 . The method according to  claim 21 , wherein the specified criterion comprises the results of the data capture being valid. 
     
     
         23 . The method according to  claim 21 , wherein changing the phase value of the clock signal further comprises selecting the phase value by evaluating a range of phase values using a set of windows. 
     
     
         24 . The method according to  claim 23 , wherein evaluating the range of phase values using the set of windows further comprises evaluating each window in the set of windows to determine a pass condition or a fail condition. 
     
     
         25 . The method according to  claim 21 , wherein selecting the phase value of the clock signal further comprises:
 changing the phase value of the clock signal over a range of phase values; and   capturing data for each phase value in the range of phase values.   
     
     
         26 . The method according to  claim 25 , further comprising evaluating the data captured for each phase value in the range of phase values. 
     
     
         27 . The method according to  claim 25 , wherein changing the phase value of the clock signal is performed over a 360-degree range of phase values. 
     
     
         28 . The method according to  claim 25 , wherein changing the phase value of the clock signal is performed over a 720-degree range of phase values. 
     
     
         29 . An apparatus, comprising a memory clocked by a clock signal with a phase value, wherein the phase value of the clock signal is swept during a data capture operation in order to results of the data capture operation to meet a specified criterion. 
     
     
         30 . The apparatus according to  claim 29 , wherein the phase value of the clock signal is swept over a 360-degree range of phase values. 
     
     
         31 . The apparatus according to  claim 29 , wherein the phase value of the clock signal is swept over a 720-degree range of phase values. 
     
     
         32 . The apparatus according to  claim 29 , wherein the phase value of the clock signal is swept over an (M*360)-degree range of phase values, where M is an integer. 
     
     
         33 . The apparatus according to  claim 29 , further comprising a phase locked loop (PLL) adapted to generate an output signal from which the clock signal is derived. 
     
     
         34 . The apparatus according to  claim 29 , further comprising a selectable vector size shift register that changes a phase of the clock signal to sweep the phase of the clock signal. 
     
     
         35 . The apparatus according to  claim 34 , wherein the shift register is serially loaded. 
     
     
         36 . The apparatus according to  claim 34 , wherein the shift register is loaded in parallel. 
     
     
         37 . The apparatus according to  claim 34 , wherein the shift register changes the phase of the clock signal by using a set of windows. 
     
     
         38 . The apparatus according to  claim 37 , wherein a window from the set of windows that has a largest size is selected. 
     
     
         39 . The apparatus according to  claim 29 , wherein the data capture operation comprises a DQS-based data capture operation. 
     
     
         40 . The apparatus according to  claim 29 , wherein the data capture operation comprises a calibrated capture clock data capture data capture operation.