Electrically Erasable Programmable Non-Volatile Memory

Abstract

In an embodiment of the invention, a method of fabricating a floating-gate PMOSFET (p-type metal-oxide semiconductor field-effect transistor) is disclosed. A silicide blocking layer (e.g. oxide, nitride) is used not only to block areas from being silicided but to also form an insulator on top of a poly-silicon gate. The insulator along with a top electrode (control gate) forms a capacitor on top of the poly-silicon gate. The poly-silicon gate also serves at the bottom electrode of the capacitor. The capacitor can then be used to capacitively couple charge to the poly-silicon gate. Because the poly-silicon gate is surrounded by insulating material, the charge coupled to the poly-silicon gate may be stored for a long period of time after a programming operation.

1 . A floating-gate p-type MOSFET (metal-oxide semiconductor field-effect transistor) comprising:
 a poly-silicon gate over a channel region; wherein the poly-silicon gate only makes physical contact with insulators; wherein the channel region has a length and is located in an Nwell;   an p-type source region formed in the Nwell region, wherein the p-type source region is proximate to a first end of the channel region;   an p-type drain region formed in the Nwell region, wherein the p-type drain region is proximate to a second end of the channel region;   a first field oxide region formed proximate to the p-type source region;   a second field oxide region formed proximate to the p-type drain region;   an insulator having a substantially constant thickness located between the poly-silicon gate and the channel region;   a side-wall oxide formed on sides of the poly-silicon gate;   a side-wall nitride formed on the side-wall oxide;   a silicide-blocking material entirely covering the poly-silicon gate, a first portion of the source region and a first portion of the drain region; wherein the silicide-blocking material is covered with a nitride layer; wherein the nitride layer is covered with a conductive material.   
     
     
         2 . The floating-gate p-type MOSFET of  claim 1  wherein the conductive material is selected from a group consisting of TaN, TiN and poly-silicon. 
     
     
         3 . The floating-gate p-type MOSFET of  claim 1  wherein the insulator is selected from a group consisting of an oxide, a nitride, and an oxide/nitride combination. 
     
     
         4 . The floating-gate p-type MOSFET of  claim 1  wherein the floating-gate p-type MOSFET is programmed by applying approximately −6.5 volts on the drain of the floating-gate p-type MOSFET for approximately 100 micro-seconds. 
     
     
         5 . The floating-gate p-type MOSFET of  claim 1  wherein the floating-gate p-type MOSFET is erased by applying approximately 8 volts on the NW of the floating-gate p-type MOSFET and −7 volts on the conductive layer. 
     
     
         6 . A method of fabricating a floating-gate p-type MOSFET comprising:
 forming a first and a second thick oxide region on a p-type substrate;   implanting a first and a second Pwell region below the first and second thick oxide region respectively;   implanting an Nwell region between the first and second thick oxide regions and the first and second Pwells;   growing a gate insulation on the Nwell region;   depositing poly-silicon on the gate insulation;   etching the poly-silicon to form a poly-silicon gate;   forming oxide side-walls on sides of the poly-silicon gate;   forming nitride side-walls on the oxide side-walls;   implanting an p-type dopant into the Nwell on both sides of the nitride side-walls forming a source and a drain;   forming a silicide-blocking layer over the poly-silicon gate, the oxide side-walls, the nitride walls, a first portion of the source and a first portion of the drain;   forming a silicide on a second portion of the source and on a second portion of the drain;   forming a nitride layer over the silicide-blocking layer, the poly-silicon gate, the oxide side-walls, the nitride walls, the first portion of the source and the first portion of the drain;   forming a conductive layer over the nitride layer;   forming metal contacts on the second portion of the source and on the second portion of the drain.   
     
     
         7 . The method of  claim 6  wherein the insulator is selected from a group consisting of an oxide, a nitride, and an oxide/nitride combination. 
     
     
         8 . The non-volatile anti-fuse memory cell of  claim 6  wherein the insulator is a high K dielectric insulator. 
     
     
         9 . The method of  claim 6  wherein the thick oxide region is selected from a group consisting of a swallow-trench isolation and locos (local oxidation of silicon) isolation. 
     
     
         10 . The method of  claim 6  wherein the conductive layer is selected from a group consisting of TaN, TiN and poly-silicon. 
     
     
         11 . A method of fabricating a floating-gate p-type MOSFET, a p-type MOSFET and an analog capacitor concurrently comprising:
 forming a first, a second, a third, a fourth, and a fifth thick oxide region on an p-type substrate;   implanting a first and a second Pwell region below the first and the second thick oxide region respectively and a third and a fourth Pwell region below the third and the fourth thick oxide region respectively;   implanting a first Nwell region between the first and the second thick oxide regions and a second Nwell region between the third and the fourth thick oxide region;   growing a gate insulation on the first and second Nwell regions and on the fifth thick oxide region;   depositing poly-silicon on the gate insulation;   etching the poly-silicon to form a first, a second and a third poly-silicon portion;   forming oxide side-walls on sides of the first, the second and the third poly-silicon portions;   forming nitride side-walls on the oxide side-walls;   implanting an p-type dopant into the first and the second Nwells forming a first and a second source and a first and a second drain;   forming a silicide-blocking layer over the first poly-silicon portion, the oxide side-walls of the first poly-silicon portion, the nitride walls of the first poly-silicon portion, a first portion of the first source and a first portion of the first drain;   forming a silicide on a second portion of the first source, on a second portion of the first drain, on a first portion of the second source, on a first portion of the second drain, on the second poly-silicon portion, and on the third poly-silicon portion;   forming a nitride layer over the silicide-blocking layer and over the silicide on the third poly-silicon portion;   forming a conductive layer over the nitride layer;   forming metal contacts on the second portion of the first source, the second portion of the first drain, the first portion of the second source, and the first portion of the second drain.   
     
     
         12 . The method of  claim 11  wherein the insulator is selected from a group consisting of an oxide, a nitride, and an oxide/nitride combination. 
     
     
         13 . The non-volatile anti-fuse memory cell of  claim 11  wherein the insulator is a high K dielectric insulator. 
     
     
         14 . The method of  claim 11  wherein the thick oxide region is selected from a group consisting of a swallow-trench isolation and locos (local oxidation of silicon) isolation. 
     
     
         15 . The method of  claim 11  wherein the conductive layer is selected from a group consisting of TaN, TiN and poly-silicon. 
     
     
         16 . A system comprising:
 at least one integrated circuit, the at least one integrated circuit comprising:
 at least one programmable non-volatile EEPROM memory cell, the at least one programmable non-volatile EEPROM memory cell comprising:
 at least one floating-gate p-type MOSFET comprising:
 a poly-silicon gate over a channel region; wherein the poly-silicon gate only makes physical contact with insulators; wherein the channel region has a length and is located in an Nwell; 
 an p-type source region formed in the Nwell region, wherein the p-type source region is proximate to a first end of the channel region; 
 
 
   an p-type drain region formed in the Nwell region, wherein the p-type drain region is proximate to a second end of the channel region;
 a first field oxide region formed proximate to the p-type source region; 
 a second field oxide region formed proximate to the p-type drain region; 
 an insulator having a substantially constant thickness located between the poly-silicon gate and the channel region; 
 a side-wall oxide formed on the sides of the poly-silicon gate; 
 a side-wall nitride formed on the side-wall oxide; 
 a silicide-blocking material entirely covering the poly-silicon gate, a first portion of the source region and a first portion of the drain region; wherein the silicide-blocking material is covered with a nitride layer; wherein the nitride layer is covered with a conductive material. 
   
     
     
         17 . The system of  claim 16  wherein the system is selected from a group consisting of a video game console, a mobile phone, a radio-frequency identification tag, an implantable medical device, a high-definition multimedia interface and an automotive electronics device. 
     
     
         18 . A method of fabricating a floating-gate n-type MOSFET comprising:
 forming a first and a second thick oxide region on an n-type substrate;   implanting a first and a second Nwell region below the first and second thick oxide region respectively;   implanting an Pwell region between the first and second thick oxide regions and the first and second Nwells;   growing a gate insulation on the Pwell region;   depositing poly-silicon on the gate insulation;   etching the poly-silicon to form a poly-silicon gate;   forming oxide side-walls on sides of the poly-silicon gate;   forming nitride side-walls on the oxide side-walls;   implanting an n-type dopant into the Pwell on both sides of the nitride side-walls forming a source and a drain;   forming a silicide-blocking layer over the poly-silicon gate, the oxide side-walls, the nitride walls, a first portion of the source and a first portion of the drain;   forming a silicide on a second portion of the source and on a second portion of the drain;   forming a nitride layer over the silicide-blocking layer, the poly-silicon gate, the oxide side-walls, the nitride walls, the first portion of the source and the first portion of the drain;   forming a conductive layer over the nitride layer;   forming metal contacts on the second portion of the source and the second portion of the drain.   
     
     
         19 . The method of  claim 18  wherein the insulator is selected from a group consisting of an oxide, a nitride, and an oxide/nitride combination. 
     
     
         20 . The non-volatile anti-fuse memory cell of  claim 18  wherein the insulator is a high K dielectric insulator.