Multi-partition architecture for memory

Abstract

A multiple partition memory and architecture for concurrent operations reduces circuit overhead by providing a common read sense amplifier and program path for multiple partitions. Long separate datalines for read and algorithm operations allow concurrent operation and blockout of multiple operations in a single block of the memory.

1 . A multiple partition memory architecture, comprising:
 a plurality of partitions, each partition comprising a plurality of memory blocks of memory cells;   a plurality of groups of at least two partitions;   a plurality of program path and sense path circuits, one common program path and send path circuit for each of the plurality of groups; and   separate pluralities of read and algorithm datalines, each of the plurality of read and algorithm datalines spanning all of one of the plurality of groups.   
     
     
         2 . The memory architecture of  claim 1 , and further comprising:
 a plurality of read pass gates, each read pass gate selectively connectable between one of the plurality of read datalines and a bitline of a memory block.   
     
     
         3 . The memory architecture of  claim 1 , and further comprising:
 a plurality of algorithm pass gates, each algorithm pass gate selectively connectable between one of the plurality of algorithm datalines and a bitline of a memory block.   
     
     
         4 . The memory architecture of  claim 1 , and further comprising:
 a plurality of read pass gates, each read pass gate selectively connectable between one of the plurality of read datalines and a bitline of a memory block; and   a plurality of algorithm pass gates, each algorithm pass gate selectively connectable between one of the plurality of algorithm datalines and a bitline of a memory block.   
     
     
         5 . The memory architecture of  claim 1 , and further comprising:
 a single algorithm sense amplifier for each I/O of the memory architecture, wherein the single algorithm sense amplifier is selectively connectable to one of the algorithm datalines.   
     
     
         6 . A flash memory architecture, comprising:
 a plurality of partitions, each partition comprising a plurality of memory blocks of memory cells;   a plurality of groups of at least two partitions;   a plurality of program path and sense path circuits, one common program path and sense path circuit for each of the plurality of groups; and   separate pluralities of read and algorithm datalines, each of the plurality of read and algorithm datalines spanning all of one of the plurality of groups.   
     
     
         7 . The memory architecture of  claim 6 , and further comprising:
 a plurality of read pass gates, each read pass gate selectively connectable between one of the plurality of read datalines and a bitline of a memory block.   
     
     
         8 . The memory architecture of  claim 6 , and further comprising:
 a plurality of algorithm pass gates, each algorithm pass gate selectively connectable between one of the plurality of algorithm datalines and a bitline of a memory block.   
     
     
         9 . The memory architecture of  claim 6 , and further comprising:
 a plurality of read pass gates, each read pass gate selectively connectable between one of the plurality of read datalines and a bitline of a memory block; and   a plurality of algorithm pass gates, each algorithm pass gate selectively connectable between one of the plurality of algorithm datalines and a bitline of a memory block.   
     
     
         10 . The memory architecture of  claim 6 , and further comprising:
 a single algorithm sense amplifier for each I/O of the memory architecture, wherein the single algorithm sense amplifier is selectively connectable to one of the algorithm datalines.   
     
     
         11 . The memory architecture of  claim 6 , wherein the non-volatile memory cells are floating gate memory cells. 
     
     
         12 . A flash memory, comprising:
 an array of non-volatile memory cells having a multiple partition memory architecture, comprising:
 a plurality of partitions, each partition comprising a plurality of memory blocks of memory cells; 
 a plurality of groups of at least two partitions; and 
   control circuitry to read, write and erase the memory cells, wherein the control circuitry further comprises:
 a plurality of program path and sense path circuits, one common program path and sense path circuit for each of the plurality of groups; and 
 separate pluralities of read and algorithm datalines, each of the plurality of read and algorithm datalines spanning all of one of the plurality of groups. 
   
     
     
         13 . The memory of  claim 12 , and further comprising:
 a plurality of read pass gates, each read pass gate selectively connectable between one of the plurality of read datalines and a bitline of a memory block.   
     
     
         14 . The memory of  claim 12 , and further comprising:
 a plurality of algorithm pass gates, each algorithm pass gate selectively connectable between one of the plurality of algorithm datalines and a bitline of a memory block.   
     
     
         15 . The memory of  claim 12 , and further comprising:
 a plurality of read pass gates, each read pass gate selectively connectable between one of the plurality of read datalines and a bitline of a memory block; and   a plurality of algorithm pass gates, each algorithm pass gate selectively connectable between one of the plurality of algorithm datalines and a bitline of a memory block.   
     
     
         16 . The memory of  claim 12 , and further comprising:
 a single algorithm sense amplifier for each I/O of the memory architecture, wherein the single algorithm sense amplifier is selectively connectable to one of the algorithm datalines.   
     
     
         17 . A processing system, comprising:
 a processor; and   a memory coupled to the processor to store data provided by the processor and to provide data to the processor, the memory comprising:   an array of memory cells addressable by address circuitry and input output circuitry, having a multiple partition memory architecture, comprising:   a plurality of partitions of memory cells;   a plurality of groups of at least two partitions; and   control circuitry to read, write and erase the memory cells;   wherein the control circuitry further comprises:
 a plurality of program path and sense path circuits, one common program path and sense path circuit for each of the plurality of groups; and 
 separate pluralities of read and algorithm datalines, each of the plurality of read and algorithm datalines spanning all of one of the plurality of groups. 
   
     
     
         18 . A memory device comprising:
 an array of memory cells having a multiple partition memory architecture, comprising:
 a plurality of partitions of memory cells; 
 a plurality of groups of at least two partitions; and 
   control circuitry to read, write and erase the memory cells;   wherein the control circuitry further comprises:
 a plurality of program path and sense path circuits, one common program path and sense path circuit for each of the plurality of groups; and 
 separate pluralities of read and algorithm datalines, each of the plurality of read and algorithm datalines spanning all of one of the plurality of groups.