Semiconductor device having a super junction structure and method of manufacturing the same

Abstract

A semiconductor device having a super junction and a method of manufacturing the semiconductor device capable of obtaining a high breakdown voltage are provided, whereby charge balance of the super junction is further accurately controlled in the semiconductor device that is implemented by an N-type pillar and a P-type pillar. The semiconductor device includes a semiconductor substrate; and a blocking layer including a first conductive type pillar and a second conductive type pillar that extend in a vertical direction on the semiconductor substrate and that are alternately arrayed in a horizontal direction, wherein, in the blocking layer, a density profile of a first conductive type dopant may be uniform in the horizontal direction, and the density profile of the first conductive type dopant may vary in the vertical direction.

1 . A semiconductor device having a super junction, the semiconductor device comprising:
 a semiconductor substrate; and   a blocking layer comprising a first conductive type pillar and a second conductive type pillar that extend in a vertical direction on the semiconductor substrate and that are alternately arrayed in a horizontal direction,   wherein, in the blocking layer, a density profile of a first conductive type dopant is uniform in the horizontal direction, and the density profile of the first conductive type dopant varies in the vertical direction.   
     
     
         2 . The semiconductor device of  claim 1 , wherein the density profile of the first conductive type dopant varies in the vertical direction according to a predetermined period. 
     
     
         3 . The semiconductor device of  claim 1 , wherein a high-density portion and a low-density portion in the density profile of the first conductive type dopant are repeated in the vertical direction. 
     
     
         4 . The semiconductor device of  claim 1 , wherein a side surface of the first conductive type pillar and a side surface of the second conductive type pillar contact each other, whereby the side surfaces have opposite curves. 
     
     
         5 . The semiconductor device of  claim 1 , further comprising a first conductive type epi-layer formed on the semiconductor substrate. 
     
     
         6 . The semiconductor device of  claim 1 , wherein the semiconductor substrate comprises a high density N-type substrate, the first conductive type pillar comprises an N-type pillar, and the second conductive type pillar comprises a P-type pillar. 
     
     
         7 . The semiconductor device of  claim 1 , further comprising:
 a gate insulating layer formed on the first conductive type pillar;   a gate electrode formed on the gate insulating layer;   a body layer formed in an upper region of the second conductive type pillar;   at least one source region formed in the body layer; and   a source electrode formed on the body layer and electrically connected to the at least one source region,   wherein the body layer is formed at both sides below the gate electrode, and both end portions of the gate electrode overlap with a portion of the body layer.   
     
     
         8 . The semiconductor device of  claim 1 , wherein the first and second conductive type pillars comprise a horizontal cross-section structure comprising a stripe structure, a circular structure, or a cellular structure in which the first conductive type pillar surrounds the second conductive type pillar. 
     
     
         9 . The semiconductor device of  claim 8 , wherein, when the first and second conductive type pillars comprise the cellular structure, the first conductive type pillars are connected to one another as one body. 
     
     
         10 . The semiconductor device of  claim 1 , further comprising a termination first conductive type pillar and a termination second conductive type pillar that are formed on the semiconductor substrate outside a region in which the blocking layer is formed. 
     
     
         11 . A semiconductor device having a super junction, the semiconductor device comprising:
 a semiconductor substrate; and   a blocking layer comprising a first conductive type pillar and a second conductive type pillar that are alternately arrayed in a horizontal direction on the semiconductor substrate,   wherein, in the blocking layer, first conductive type dopant density varies according to heights in a vertical direction, and the first conductive type dopant density is uniform in the horizontal direction at the same height.   
     
     
         12 . The semiconductor device of  claim 11 , wherein the first conductive type dopant density varies in the vertical direction according to a predetermined period. 
     
     
         13 . A method of manufacturing a semiconductor device having a super junction, the method comprising:
 preparing a semiconductor substrate; and   forming a blocking layer comprising a first conductive type pillar and a second conductive type pillar that extend in a vertical direction on the semiconductor substrate and that are alternately arrayed in a horizontal direction,   wherein the blocking layer is formed by performing a whole surface-implanting operation by using a first conductive type dopant.   
     
     
         14 . The method of  claim 13 , wherein, due to the whole surface-implanting operation, a density profile of the first conductive type dopant is uniform in the horizontal direction in the blocking layer. 
     
     
         15 . The method of  claim 13 , wherein the forming of the blocking layer comprises:
 forming a stack epi-layer on the semiconductor substrate, wherein the stack epi-layer comprises at least two undoped epi-layers, and a first conductive type implant layer and a second conductive type implant layer that are formed on an upper region of at least one of the at least two undoped epi-layers; and   forming the first conductive type pillar and the second conductive type pillar by diffusing a dopant of the first conductive type implant layer and a dopant of the second conductive type implant layer to the at least two undoped epi-layers by performing a thermal treatment.   
     
     
         16 . The method of  claim 15 , wherein, due to the diffusing, a density profile of the first conductive type dopant varies in the vertical direction in the blocking layer. 
     
     
         17 . The method of  claim 16 , wherein a high-density portion and a low-density portion in the density profile of the first conductive type dopant are repeated in the vertical direction. 
     
     
         18 . The method of  claim 15 , wherein the forming of the stack epi-layer comprises:
 forming an undoped epi-layers on the semiconductor substrate;   forming the first conductive type implant layer by implanting a first conductive type dopant in entire top surfaces of the undoped epi-layers;   forming the second conductive type implant layer by implanting a second conductive type dopant in a predetermined portion of the first conductive type implant layer; and   repeating the forming of the undoped epi-layers through the forming of the second conductive type implant layer.   
     
     
         19 . The method of  claim 18 , further comprising:
 forming an undoped epi-layer or a first conductive type epi-layer on the first and second conductive type implant layers that are uppermost layers;   sequentially forming the undoped epi-layer and the first conductive type epi-layer on the first and second conductive type implant layers that are the uppermost layers; or   forming a top undoped epi-layer on the first and second conductive type implant layers that are the uppermost layers, and then implanting a first conductive type dopant in an upper region of the top undoped epi-layer.   
     
     
         20 . The method of  claim 18 , wherein a thickness of at least one undoped epi-layer from among a plurality of the undoped epi-layers is different. 
     
     
         21 . The method of  claim 18 , wherein one of first and second conductive type implant layers having different dopant density is formed in at least one undoped epi-layer from among a plurality of the undoped epi-layers. 
     
     
         22 . The method of  claim 15 , further comprising forming a first conductive type epi-layer on the semiconductor substrate. 
     
     
         23 . The method of  claim 15 , wherein a thickness and an amount of dopant of each of the first conductive type implant layer and the second conductive type implant layer is defined according to Equation 1 below for the super junction
     Nn× ½ Wn=Np× ½ Wp   Equation (1)
   where Nn and Np respectively indicate impurity densities of the first conductive type pillar and the second conductive type pillar, and Wn and Wp respectively indicate widths of the first conductive type pillar and the second conductive type pillar.   
     
     
         24 . The method of  claim 13 , further comprising:
 forming a gate oxide layer on the first conductive type pillar;   forming a gate electrode on the gate oxide layer;   forming a body layer in an upper region of the second conductive type pillar;   forming at least one source region in the body layer; and   forming a source electrode electrically connected to the at least one source region.   
     
     
         25 . The method of  claim 13 , wherein the semiconductor substrate is divided into an active region and a termination region that surrounds the active region, and
 a termination first conductive type pillar and a termination second conductive type pillar on the semiconductor substrate of the termination region are formed when the blocking layer is formed.   
     
     
         26 . A method of manufacturing a semiconductor device having a super junction, the method comprising:
 preparing a semiconductor substrate;   forming an undoped epi-layer on the semiconductor substrate;   forming a first conductive type implant layer by implanting a first conductive type dopant in an entire top surface of the undoped epi-layer;   forming a second conductive type implant layer by implanting a second conductive type dopant in a predetermined portion of the first conductive type implant layer;   repeating the forming of the undoped epi-layer through the forming of the second conductive type implant layer; and   forming a first conductive type pillar and a second conductive type pillar by diffusing a dopant of the first conductive type implant layer and a dopant of the second conductive type implant layer to the undoped epi-layer by performing a thermal treatment.   
     
     
         27 . The method of  claim 26 , wherein the first conductive type pillar and the second conductive type pillar form a blocking layer by extending in a vertical direction, on the semiconductor substrate and by being alternately arrayed in a horizontal direction, on the semiconductor substrate, and
 the blocking layer is formed whereby density of the first conductive type dopant varies according to heights in the vertical direction, and the density of the first conductive type dopant is uniform in the horizontal direction at the same height.   
     
     
         28 . The method of  claim 26 , further comprising forming a first conductive type epi-layer on the semiconductor substrate. 
     
     
         29 . The method of  claim 26 , before the forming of the first conductive type pillar and the second conductive type pillar, further comprising:
 forming an undoped epi-layer or a first conductive type epi-layer on the first and second conductive type implant layers that are uppermost layers;   sequentially forming the undoped epi-layer and the first conductive type epi-layer on the first and second conductive type implant layers that are the uppermost layers; or   forming a top undoped epi-layer on the first and second conductive type implant layers that are the uppermost layers, and then implanting a first conductive type dopant in an upper region of the top undoped epi-layer.