Digital signal routing circuit

Abstract

An integrated circuit for digital signal routing. Signal routing is achieved by means of a multiply-accumulate block, which takes data from one or more data source and, after any required scaling, generates output data for a data destination. The multiply-accumulate block operates on a time division multiplexed basis, so that multiple signal paths can be processed within one period of the sample clock. Each signal path has a respective sample clock rate, and paths with different sample clock rates can be routed through the multiply-accumulate block on a time division multiplexed basis independently of each other. Thus, speech signals at 8 kHz or 16 kHz can be processed concurrently with audio data at 44 kHz or 48 kHz.

1 . An integrated circuit comprising:
 a digital mixing core configurable to combine a plurality of streams of audio data samples, said digital mixing core comprising:   a plurality of digital signal processing blocks wherein each of said digital signal processing blocks comprises a source port and a destination port, said digital signal processing blocks each being configurable to: receive streams of audio data samples at a respective sample clock rate at said destination port, process the received streams of audio data samples, and transmit the processed streams of audio data samples at said respective sample clock rate from said source port;   a clock generator configurable to generate at least a data clock; and   a mixing fabric, said mixing fabric comprising:   a mixer comprising a multiplier-accumulator, said multiplier-accumulator comprising a multiplier-accumulator input and a multiplier-accumulator output, said mixer being configurable to combine audio data samples in response to said data clock;   a source selector comprising a plurality of source selector inputs and a source selector output, said source selector output being connected to said multiplier-accumulator input,   a plurality of source buffers each respectively connected between a said source port and a said source selector input, each source buffer configurable to temporarily store a sample of a respective said transmitted stream of audio data samples,   wherein said source selector is configurable in response to a source selector control signal to couple any one of said respective source buffers to said multiplier-accumulator input;   a destination selector comprising a destination selector input and a plurality of destination selector outputs, said destination selector input being connected to said multiplier-accumulator output,   a plurality of destination buffers each respectively connected between a said destination port and a said destination selector output, each destination buffer being configurable to temporarily store a sample of a respective stream of said combined audio data samples,   wherein said destination selector is configurable in response to a destination selector control signal to couple any one of said respective destination buffers to said multiplier-accumulator output; and   
       programmable storage circuitry configurable to store a plurality of configuration data sets, each one of said plurality of configuration data sets respectively defining a signal path, said signal path comprising at least two source ports and a destination port; and
 a controller coupled to said programmable storage circuitry, said source selector and said destination selector, said controller being configured to receive a plurality of configuration data and control said source and destination selectors with respective source and destination selector control signals to establish on a time-division-multiplexed basis in response to said data clock each one of a plurality of respective said defined signal paths within each period of a respective sample clock. 
 
     
     
         2 . An integrated circuit as claimed in  claim 1 , wherein said programmable storage circuitry is configurable to store a second plurality of configuration data sets, each one of said second plurality of configuration data sets respectively defining a signal path, said signal path comprising one source port and a destination port, and wherein, when a signal path comprises one source port, each destination buffer is also configurable to temporarily store a sample of a respective stream of output audio data samples derived from the stream of audio data samples received from said one source port. 
     
     
         3 . An integrated circuit as claimed in  claim 1 , wherein the programmable storage circuitry is configurable such that each of said configuration data sets identifies at least one scaling factor,
 said multiplier-accumulator mixer being configurable to multiply the or each received audio data sample by a respective scaling factor.   
     
     
         4 . An integrated circuit as claimed in  claim 1 , wherein the integrated circuit further comprises a plurality of digital inpu't interfaces, providing a further plurality of respective signal source ports. 
     
     
         5 . An integrated circuit as claimed in  claim 1 , wherein the integrated circuit further comprises a plurality of digital output interfaces, providing a further plurality of respective signal destination ports. 
     
     
         6 . An integrated circuit as claimed in  claim 1 , wherein the integrated circuit further comprises a plurality of digital input interfaces, providing a further plurality of respective signal source ports, wherein the integrated circuit further comprises a plurality of digital output interfaces, providing a further plurality of respective signal destination ports, and wherein the controller is configurable to define a direct signal path from one of said digital input interfaces through the multiplier—accumulator to one of said digital output interfaces. 
     
     
         7 . An integrated circuit as claimed in  claim 1 , wherein the programmable storage circuitry is configurable to store in each of the plurality of configuration data sets a respective data sample rate for the signal path, the data sample rates of said signal paths being configurable independently of each other. 
     
     
         8 . An integrated circuit as claimed in  claim 1 , wherein each one of said plurality of configuration data sets defines a respective sample rate. 
     
     
         9 . An integrated circuit as claimed in  claim 8 , wherein the sample rate for each signal path is programmable independently. 
     
     
         10 . An integrated circuit as claimed in  claim 8 , wherein the programmable storage circuitry is configurable to store at a single location data defining the sample rate for all destination ports on at least one signal processing block. 
     
     
         11 . An integrated circuit as claimed in  claim 8 , wherein the programmable storage circuitry is configurable to store data indicating one of a predetermined plurality of available sample clocks. 
     
     
         12 . An integrated circuit as claimed in  claim 1 , wherein the number of signal paths that can be established within each period of a respective sample clock is much smaller than the number of signal paths required to connect all signal source ports to all signal destination ports. 
     
     
         13 . An integrated circuit as claimed in  claim 1 , wherein the controller comprises a mixer utilisation predictor, for identifying each defined signal path, for determining a number of calculations to be performed for each defined signal path in a specified time interval, and for setting the frequency of the data clock such that said number of calculations can be performed in the specified time interval. 
     
     
         14 . An integrated circuit as claimed in  claim 13 , wherein the controller is adapted to receive inputs identifying a plurality of available data clock rates, and to select the frequency of the data clock as the lowest of these available data clock rates that enables said number of calculations to be performed in the specified time interval. 
     
     
         15 . An integrated circuit as claimed in  claim 1 , wherein the controller is configured such that, at successive time intervals, the signal path that is established by the source and destination selector control signals is determined on the basis that it is the signal path that has the shortest time before an end of a period of a clock signal at the respective data sample rate. 
     
     
         16 . An integrated circuit as claimed in  claim 15 , comprising a register, for storing details of activated signal paths, identifying the or each signal source port, the signal destination port, and the respective data sample rate of each activated signal path. 
     
     
         17 . An integrated circuit as claimed in  claim 16 , comprising a down-counter associated with each available data sample rate, for maintaining a count of the time remaining before the end of a period of a clock signal at the respective data sample rate, and logic for selecting the sample rate having the shortest time before the end of a period of a clock signal at the respective data sample rate. 
     
     
         18 . An integrated circuit as claimed in  claim 17 , further comprising logic for selecting one of the signal paths having the selected sample rate. 
     
     
         19 . An integrated circuit as claimed in  claim 1 , further comprising:
 at least one additional signal processing block, connected to receive digital input signals and to provide digital output signals without passing said signals through the mixer.   
     
     
         20 . An integrated circuit as claimed in  claim 19 , comprising downsampling circuitry, for receiving the digital input signal of the additional signal processing block in parallel therewith, and for providing downsampled digital input signals at a signal source port comprised by the downsampling circuitry. 
     
     
         21 . An integrated circuit as claimed in  claim 19 , comprising upsampling circuitry, comprising a signal destination port and for providing upsampled digital output signals. 
     
     
         22 . An integrated circuit as claimed in  claim 19 , wherein the additional signal processing block is connected to receive control signals from at least one of a plurality of the first signal processing blocks. 
     
     
         23 . An integrated circuit as claimed in  claim 19 , wherein the additional signal processing block is configured to process digital input signals at a sample rate of at least 384 ksamples/second. 
     
     
         24 . An integrated circuit as claimed in  claim 19 , wherein the additional signal processing block comprises filter circuitry, for generating a noise cancellation signal from an input signal representing ambient noise. 
     
     
         25 . An integrated circuit as claimed in  claim 1 , wherein the clock generator is configured for generating a plurality of clock signals at respective different frequencies; and
 wherein the plurality of signal processing blocks each require a clock signal at a preferred frequency;   further comprising selection circuitry, configured such that each of the signal processing blocks receives said clock signal at the preferred frequency.   
     
     
         26 . An integrated circuit as claimed in  claim 25 , further comprising logic for receiving control signals generated by each of said signal processing blocks, and for allowing distribution of a clock signal only if it is the preferred frequency of one or more of the signal processing blocks. 
     
     
         27 . An integrated circuit, comprising a mixer than can be inserted into a plurality of data paths in a time division multiplexed manner, such that data that is presented to the mixer by the start of one sample clock period is available for a receiving block for the whole of the next period of the sample clock. 
     
     
         28 . An integrated circuit comprising a digital mixing core, said digital mixing core being configurable to process a plurality of streams of audio data samples, and said digital mixing core comprising:
 a plurality of digital signal processing blocks, wherein each of said digital signal processing blocks comprises a source port and a destination port, said digital signal processing blocks each being configurable to   receive a stream of audio data samples at said destination port,   process the received stream of audio data, and   transmit the processed stream of audio data from said source port;   programmable storage circuitry configurable to store a plurality of configuration data sets, wherein each one of said plurality of configuration data sets respectively defines at least two source ports and a destination port; and   mixing fabric configurable to:   establish a plurality of concurrent signal paths corresponding to said configuration data sets, and   in each signal path, to combine data from respective streams of audio data samples from said defined at least two source ports to provide a combined data stream and transmit said combined data stream to said defined destination port in accordance with a respective one of said plurality of configuration data sets.   
     
     
         29 . A integrated circuit configurable to store a plurality of configuration data sets, wherein each one of said plurality of configuration data sets respectively defines at least one source port and a destination port, and being further configurable to establish a plurality of concurrent signal paths from the at least one respective source port through the mixing core to the respective destination port in accordance with a respective one of said plurality of configuration data sets. 
     
     
         30 . An integrated circuit comprising a digital mixing core configurable to process streams of audio data samples, said digital mixing core comprising mixing fabric, said mixing fabric comprising:
 a mixer, said mixer comprising a multiplier-accumulator, said multiplier-accumulator comprising a multiplier-accumulator input and a multiplier-accumulator output;   at least first and second source data buffers each respectively configurable to repeatedly receive respective at least first and second audio data samples and repeatedly store said respective at least first and second audio data samples;   at least a first destination data buffer configurable to repeatedly store a respective at least third audio data sample and repeatedly transmit said at least third audio data sample;   said mixing fabric configurable to, repeatedly, establish at least one signal path by:   receiving a first audio data sample within a period of a sample clock;   storing said first audio data sample in a first data source buffer for the remainder of said period and for the whole of a next period of said sample clock;   receiving at least one second audio data sample within said period;   storing the or each second audio data sample in a respective second data source buffer for the remainder of said period and for the whole of said next period;   retrieving said stored first audio data sample within said next period;   multiplying said first audio data sample by a first multiplication coefficient and thus generate a first partial sum within said next period;   temporarily storing said first partial sum within said next period;   retrieving said stored at least one second audio data sample within said next period;   multiplying the or each second audio data sample by a respective second multiplication coefficient thus generating at least one respective second partial sum within said next period;   adding said first partial sum and said at least one second partial sum to generate a third audio data sample within said next period; and   storing said third audio data sample in a data destination buffer for the remainder of said next period and for the duration of a subsequent next period.   
     
     
         31 . A method of processing streams of audio data samples, said method comprising the steps of, repeatedly:
 receiving a first audio data sample within a period of a sample clock;   storing said first audio data sample in a first data source buffer for the remainder of said period and for the whole of a next period of said sample clock;   receiving at least one second audio data sample within said period;   storing the or each second audio data sample in a respective second data source buffer for the remainder of said period and for the whole of said next period;   retrieving said stored first audio data sample within said next period;   multiplying said first audio data sample by a first multiplication coefficient thus generating a first partial sum within said next period;   temporarily storing said first partial sum within said next period;   retrieving said stored at least one second audio data sample within said next period;   multiplying the or each second audio data sample by a respective second multiplication coefficient thus generating at least one respective second partial sum within said next period;   adding said first partial sum and said at least one second partial sum to generate a third audio data sample within said next period;   storing said third audio data sample in a data destination buffer for the remainder of said next period and for the duration of a subsequent next period.   
     
     
         32 . An integrated circuit comprising a multiply-accumulate block, wherein the multiply-accumulate block is configured to retrieve at least one input data sample from a respective input buffer, to multiply the or each input data sample by a respective scaling factor, and to generate an output data sample from the or each scaled input data sample within one cycle of a data sample clock, wherein each input buffer is configured to store a respective input data sample for a whole of said one cycle of the data sample clock, being a cycle after a cycle in which it is received, and wherein the output buffer is configured to store the output data sample for an entire cycle of the data sample clock after said cycle. 
     
     
         33 . An integrated circuit comprising:
 a digital mixing core configurable to mix streams of audio data samples, said digital mixing core comprising:   a plurality of digital signal processing blocks, each comprising:   one or more source ports configurable to transmit respective audio data samples at a respective sample clock rate; and   one or more destination ports configurable to receive respective audio data samples at a respective sample clock rate,   the digital mixing core further comprising:   a mixer comprising a multiply-accumulate block, said multiply-accumulate block comprising an input and an output, said mixer being configurable to combine audio data samples in response to a received data clock;   a clock generator configurable to generate at least said data clock;   a source selector configurable to couple said multiply-accumulate block input to any one of said one or more source ports; and   a destination selector configurable to couple said multiply-accumulate block output to any one of said one or more destination ports;   wherein said source and destination selectors are respectively configurable in a sequence, at the frequency of said data clock, to establish, in turn, a set of signal paths through the mixer, each comprising any one of said one or more destination ports and one or more of said one or more source ports; and   wherein the frequency of said data clock is less than that necessary to establish for every destination port, within one period of each respective sample clock, a signal path comprising every source port.   
     
     
         34 . An integrated circuit, comprising a digital mixing core, the digital mixing core comprising a plurality of signal sources and signal destinations, and at least one mixer to which the signal sources and signal destinations can be connected on a time division multiplexed basis to establish signal paths,
 wherein each signal destination requires data at a respective predetermined sample rate,   wherein the or each mixer operates at a clock frequency, and   wherein:   
       
         
           
             
               
                 
                   ∑ 
                   j 
                 
                  
                 
                     
                 
                  
                 
                   
                     m 
                     j 
                   
                   · 
                   
                     C 
                     
                       R 
                       , 
                       j 
                     
                   
                 
               
                
               
                 
                   ∑ 
                   i 
                 
                  
                 
                     
                 
                  
                 
                   
                     S 
                     
                       R 
                       , 
                       i 
                     
                   
                   · 
                   
                     N 
                     
                       S 
                       , 
                       i 
                     
                   
                   · 
                   
                     N 
                     
                       d 
                       , 
                       i 
                     
                   
                 
               
             
           
         
         where: 
         m j  is the number of mixers operating at the j th  mixer clock frequency 
         C R,j  is the j th  mixer clock frequency in use 
         S R,i  is the i th  sample rate in use in the system 
         N S,i  is the number of signal sources providing data at the i th  sample rate, and 
         N d,i  is the number of signal destinations requiring data at the n th  sample rate 
       
     
     
         35 . An integrated circuit, comprising a digital mixing core, the digital mixing core comprising a plurality of signal sources and signal destinations, and at least one mixer to which the signal sources and signal destinations can be connected on a time division multiplexed basis to establish signal paths,
 wherein each signal destination requires data at a respective predetermined sample rate,   wherein the or each mixer operates at a respective mixer clock frequency, and   wherein the or each mixer clock frequency is less than that necessary to be able to establish signal paths between every signal source and every signal destination during one period at the respective sample rates.   
     
     
         36 . A method of operation of an integrated circuit, the integrated circuit comprising:
 a digital mixing core configurable to mix streams of audio data samples, said digital mixing core comprising:   a plurality of digital signal processing blocks, each comprising:   one or more source ports configurable to transmit respective audio data samples at a respective sample clock rate; and   one or more destination ports configurable to receive respective audio data samples at a respective sample clock rate,   the digital mixing core further comprising:   a mixer comprising a multiply-accumulate block, said multiply-accumulate block comprising an input and an output, said mixer being configurable to combine audio data samples in response to a received data clock;   a clock generator configurable to generate at least said data clock;   a source selector configurable to couple said multiply-accumulate block input to any one of said one or more source ports; and   a destination selector configurable to couple said multiply-accumulate block output to any one of said one or more destination ports;   the method comprising:   configuring said source and destination selectors respectively in a sequence, at the frequency of said data clock, to establish, in turn, a set of signal paths through the mixer, each comprising any one of said one or more destination ports and one or more of said one or more source ports; and   setting the frequency of said data clock to be less than that necessary to establish for every destination port, within one period of each respective sample clock, a signal path comprising every source port.