Burst Mode Clock and Data Recovery Circuit and Method

Abstract

Burst mode clock and data recovery (BCDR) circuit and method capable of fast data recovery of passive optical network (PON) traffic. An over-sampled data stream is generated from an input burst data signal and a phase interpolator generates sampling clock signals using a reference clock and phase information. A phase estimation unit (PEU) determines a phase error in the over-sampled data streams; and a phase retrieval unit sets the phase interpolator with the respective phase information of the input burst data signal prior to reception of the input burst data signal.

1 . A burst mode clock and data recovery (BCDR) circuit, comprising:
 an over-sampler configured to oversample a burst data signal according to a plurality of sampling clock signals to provide a plurality of over-sampled data streams;   a phase interpolator configured to generate the plurality of sampling clock signals, the plurality of sampling clock signals being phase shifted utilizing a phase information corresponding to an estimated phase of the burst data signal;   a phase retrieval unit configured to provide the phase information prior to the oversampler oversampling the burst data signal; and   a pipeline configured to output a recovered data signal based on an accuracy of the plurality of sampling clock signals.   
     
     
         2 . The BCDR circuit of  claim 1 , further comprising:
 a reference clock module configured to provide a reference clock signal, wherein the phase interpolator is further configured to phase shift the plurality of sampling clock signals by a factor proportional to the reference clock signal plus a phase represented by the phase information.   
     
     
         3 . The BCDR circuit of  claim 2 , wherein the factor is a reciprocal of a number of the plurality of sampling clock signals generated by the phase interpolator. 
     
     
         4 . The BCDR of  claim 1 , further comprising:
 a digital filter configured to extract and to compare a phase from an over-sampled data stream from among the plurality of over-sampled data streams to a reference phase to determine the accuracy of the phase of the plurality of sampling clock signals.   
     
     
         5 . The BCDR circuit of  claim 1 , wherein the phase retrieval unit further comprises:
 a phase selector configured to select a source of the phase information; and   a memory configured to store the phase information.   
     
     
         6 . The BCDR circuit of  claim 5 , wherein the phase selector is further configured to select the source of the phase information from among the phase information stored in the memory or an extracted phase information determined from the plurality of over-sampled data streams. 
     
     
         7 . The BCDR circuit of  claim 6 , wherein the burst data signal is received from an optical network unit (ONU), wherein the BCDR circuit is configured to operate in a setup mode of operation during an activation procedure of the ONU, and wherein the phase selector unit is further configured to select the source of the phase information as the extracted phase information during the setup mode of operation. 
     
     
         8 . The BCDR circuit of  claim 7 , wherein the BCDR circuit is further configured to operate in a normal mode of operation after the activation procedure, and wherein the phase selector unit is further configured to select the phase information stored in the memory during the normal mode of operation. 
     
     
         9 . The BCDR circuit of  claim 1 , further comprising:
 phase estimation unit (PEU) configured to determine the accuracy of the plurality of sampling clock signals by comparing the estimated phase to a phase threshold.   
     
     
         10 . The BCDR circuit of  claim 1 , further comprising:
 a burst detector configured to control the pipeline in response to the detection of the burst data signal.   
     
     
         11 . A burst mode clock and data recovery (BCDR) circuit, comprising:
 an over-sampler configured to oversample a burst data signal according to a plurality of sampling clock signals to provide a plurality of over-sampled data streams;   a phase estimation unit (PEU) configured to provide a plurality of phase estimates corresponding to phases of the plurality of over-sampled data streams;   a digital filter configured to process the plurality of over-sampled data streams when a phase estimate from among the plurality of phase estimates is below a phase error threshold;   a phase mover configured to receive phase information from the digital filter and to provide a phase mover signal based on the phase information; and   a phase interpolator configured to generate clock signals having substantially the same phase as the burst data signal based on the phase mover signal.   
     
     
         12 . The BCDR circuit of  claim 11 , wherein the BCDR circuit is coupled to an optical line terminal (OLT) device. 
     
     
         13 . The BCDR circuit of  claim 11 , wherein the PEU is further configured to compare the phase of the plurality of phase estimates to a threshold phase to determine a plurality of phase errors. 
     
     
         14 . The BCDR circuit of  claim 11 , wherein the digital filter is further configured to disregard an over-sampled data stream from among the plurality of over-sampled data streams when a phase estimate from among the plurality of phase estimates is above the phase error threshold. 
     
     
         15 . The BCDR circuit of  claim 11 , wherein the phase mover is further configured to provide the phase mover signal based on a physical parameter of the phase interpolator. 
     
     
         16 . In an optical line terminal (OLT), a method comprising:
 receiving a plurality of data signals from an optical network unit (ONU);   sampling the plurality of data signals according to a plurality of sampling clock signals to provide a plurality of data streams; and   selecting a data stream from among the plurality of data streams corresponding to an accuracy of a phase of a sampling clock signal from among the plurality of sampling clock signals.   
     
     
         17 . The method of  claim 16 , further comprising:
 determining a phase error of a data stream from among the plurality of data streams, and wherein the step of generating comprises:   generating a sampling clock signal from among the plurality of sampling clock signals based on the phase error.   
     
     
         18 . The method of  claim 17 , wherein the step of selecting comprises: selecting the data stream from among the plurality of data streams when the phase error is below a phase error threshold. 
     
     
         19 . The method of  claim 17 , further comprising:
 calculating a sampling point based on a phase of a data stream from among the plurality of data streams, and wherein the step of generating comprises:   generating the sampling clock signal utilizing the sampling point and the phase error.   
     
     
         20 . The method of  claim 19 , further comprising:
 repeating the steps of calculating the sampling point through generating the sampling clock signal for the plurality of data streams.