Transistors for replacing metal-oxide-semiconductor field-effect transistors in nanoelectronics

Abstract

Junction field effect transistors (JFETs) are shown to be a viable replacement for metal oxide semiconductor field effect transistors (MOSFETs) for gate lengths of less than about 40 nm, providing an alternative to the gate leakage problems presented by scaled down MOSFETs. Integrated circuit designs can have complementary JFET (CJFET) logic cells substituted for existing MOSFET-based logic cells to produce revised integrated circuit designs. Integrated circuits can include JFETS where the channel comprises a wide bandgap semiconductor material and the gate comprises a narrow bandgap semiconductor material. Mixtures of JFET and MOSFET transistors can be included on an integrated circuit design.

1 .- 13 . (canceled) 
     
     
         14 . A method of designing an integrated circuit comprising:
 providing a Complementary Junction Field Effect Transistor (CJFET) cell library comprising logic cells defined using complementary junction field effect transistors;   obtaining an integrated circuit design having at least one element defined using a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) cell library based on complementary metal oxide semiconductor transistors; and   substituting a corresponding cell from the CJFET cell library for the at least one element to produce a revised integrated circuit design based on complementary junction field effect transistors.   
     
     
         15 . The method of  claim 14 , wherein the CJFET cell library includes complementary junction field effect transistors having a gate length between about 10 nm and about 30 nm. 
     
     
         16 . The method of  claim 14 , further comprising fabricating an operational integrated circuit using the revised integrated circuit design. 
     
     
         17 . The method of  claim 16 , wherein the fabricating comprises:
 providing a wafer;   fabricating a plurality of complementary pairs on the wafer, the complementary pairs comprising a junction field effect transistor, wherein fabricating the junction field effect transistor comprises:
 defining a channel region for the at least one junction field effect transistor, forming a gate of semiconducting material in contact with the channel region, and defining a source and drain adjacent to the channel by ion implantation, wherein the gate masks the channel region from ion implantation; and 
   forming interconnections between the plurality of complementary pairs to form the integrated circuit.   
     
     
         18 . The method of  claim 17 , wherein defining a channel region comprises forming a wide bandgap semiconductor into the channel region and wherein forming a gate comprises forming a narrow bandgap semiconductor into the gate. 
     
     
         19 . The method of  claim 18 , wherein the wherein the wide bandgap semiconductor material has a bandgap of greater than about 2 eV, and wherein the narrow bandgap semiconductor material has a bandgap of less than about 2 eV. 
     
     
         20 . The method of  claim 17 , further comprising forming a plurality of metal oxide semiconductor field effect transistors on the substrate.