Memory cell presetting for improved memory performance

Abstract

Memory cell presetting for improved performance including a system that includes a memory, a cache, and a memory controller. The memory includes memory lines made up of memory cells. The cache includes cache lines that correspond to a subset of the memory lines. The memory controller is in communication with the memory and the cache. The memory controller is configured to perform a method that includes scheduling a request to set memory cells of a memory line to a common specified state in response to a cache line attaining a dirty state.

1 - 18 . (canceled) 
     
     
         19 . A system comprising:
 a memory comprising memory lines, each memory line comprising a plurality of memory cells;   a cache comprising cache lines corresponding to a subset of the memory lines; and   a memory controller in communication with the memory and the cache, the memory controller configured to perform a method that comprises scheduling a request to set memory cells of a memory line to a common specified state in response to a cache line attaining a dirty state.   
     
     
         20 . The system of  claim 19 , wherein the method further comprises:
 receiving a read request at the memory controller;   determining whether the read request can be serviced faster by temporarily canceling a request to set the cells of a memory line to a specified state;   canceling the request to set the cells of the memory line to a common specified state responsive to determining that the read request can be serviced faster by temporarily canceling a request to set the cells of the memory line to a common specified state; and   reinitiating the request to set the cells of the memory line to a common specified state responsive to the canceling and to a completion of the read request.   
     
     
         21 . The system of  claim 19 , wherein the scheduling a request comprises placing the request on a queue, wherein the request is not scheduled when the queue is full. 
     
     
         22 . The system of  claim 19 , wherein the scheduling a request comprises placing the request on a queue, wherein the request is postponed when the queue is full. 
     
     
         23 . The system of  claim 20 , wherein determining is responsive to a state of the request to set the cells of the memory line to the specified state. 
     
     
         24 - 25 . (canceled)