Method and device for detecting possible corruption of sector protection information of a non-volatile memory stored in an on board volatile memory array at power-on

Abstract

A non-volatile memory device includes addressable sectors and an ancillary volatile memory array. The ancillary volatile memory array stores protection information in the addressable sectors that is not accessible to users of the memory. The protection information is downloaded in the memory array at every power-on of the memory device. The memory array includes at least two additional columns containing preset logic information physically adjacent to the columns containing the downloaded information. A logic circuit is input with the logic information read from the additional check columns for checking the integrity of the preset logic information content of the check columns. An integrity check signal is output by the logic circuit.

1 . A method, comprising:
 reading protection information for an addressable sector of a non-volatile memory from a volatile memory space corresponding to the addressable sector;   reading preset logic information from check columns of the volatile memory space;   verifying the preset logic information with an integrity check block; and   allowing modification of data in the addressable sector of the non-volatile memory according to the state of the protection information when the preset logic information is verified with the integrity check block.   
     
     
         2 . The method of  claim 1 , wherein the check columns contain complementary preset logic information. 
     
     
         3 . The method of  claim 2 , wherein the preset logic information corresponding to each row of the volatile memory space that has a row address with a common least significant bit includes identical logic values. 
     
     
         4 . The method of  claim 1 , and further comprising:
 preventing modification of data in the addressable sector when the loaded preset logic information is not verified.   
     
     
         5 . The method of  claim 4 , wherein preventing modification of data in the addressable sector comprises disabling a data modification circuit, with respect to a modification command pertaining to the addressable sector, when the preset logic information has any set of values other than the preset logic information from the dedicated memory space. 
     
     
         6 . The method of  claim 4 , and further comprising:
 loading new protection information for the addressable sector of the non-volatile memory from a non-volatile memory space not accessible to external users to the volatile memory space when the loaded preset logic information is not verified.   
     
     
         7 . A method, comprising:
 loading protection information for an addressable sector of a non-volatile memory device from a dedicated non-volatile memory space; and   checking the protection information for integrity when modification of data stored in the addressable sector is attempted.   
     
     
         8 . The method of  claim 7 , and further comprising:
 allowing modification of data in the addressable sector when the protection information is verified.   
     
     
         9 . The method of  claim 8 , and further comprising:
 verifying the protection information by loading the protection information into a volatile protection information sector, loading preset logic information into check columns of the volatile protection information sector, and verifying the loaded preset logic information with an integrity check block.   
     
     
         10 . The method of  claim 8 , wherein loading present logic information into the check columns comprises loading complementary preset logic information in the check columns 
     
     
         11 . The method of  claim 7 , wherein checking the protection information for integrity comprises:
 loading preset logic information into check columns to a volatile memory space; and   verifying the loaded preset logic information.   
     
     
         12 . The method of  claim 11 , and further comprising:
 preventing modification of data in the addressable sector when the loaded preset logic information is not verified.   
     
     
         13 . The method of  claim 12 , wherein preventing modification of data in the addressable sector comprises disabling a data modification circuit, with respect to a modification command pertaining to the addressable sector, when the loaded preset logic information is not verified. 
     
     
         14 . The method of  claim 13 , and further comprising:
 loading new protection information for the addressable sector of the non-volatile memory from a non-volatile memory space not accessible to external users to the volatile memory space when the loaded preset logic information is not verified.   
     
     
         15 . A method, comprising:
 reading protection information for an addressable sector of a non-volatile memory device from a volatile memory space; and   checking the protection information for integrity when modification of data stored in the addressable sector is attempted.   
     
     
         16 . The method of  claim 15 , wherein checking the protection information comprises:
 reading preset logic information programmed into a pair of check columns of the volatile memory space;   verifying the preset logic information with an integrity check block; and   allowing modification of data in the addressable sector according to the protection information when the preset logic information is verified.   
     
     
         17 . The method of  claim 16 , and further comprising:
 loading new protection information for the addressable sector of the non-volatile memory from a non-volatile memory space not accessible to external users to the volatile memory space.   
     
     
         18 . A memory device, comprising:
 a non-volatile memory space inaccessible to an external user;   an addressable memory sector of non-volatile memory cells; and   a protection information sector of non-volatile memory cells associated with the addressable memory sector of non-volatile memory cells; wherein the memory verifies protection information in the protection information sector before allowing modification of data in the addressable memory sector.   
     
     
         19 . The memory device of  claim 18 , wherein the protection information sector comprises an array of memory cells for protection information, and at least two check columns for preset logic information. 
     
     
         20 . The memory device of  claim 18 , wherein the at least two check columns comprise a plurality of pairs of check columns to store the check information, the plurality of pairs of check columns being spatially distributed among columns of the protection information sector.