Transistor and method of forming the transistor so as to have reduced base resistance

Abstract

Disclosed is a transistor structure, having a completely silicided extrinsic base for reduced base resistance R b . Specifically, a metal silicide layer covers the extrinsic base, including the portion of the extrinsic base that extends below the upper portion of a T-shaped emitter. One exemplary technique for ensuring that the metal silicide layer covers this portion of the extrinsic base requires tapering the upper portion of the emitter. Such tapering allows a sacrificial layer below the upper portion of the emitter to be completely removed during processing, thereby exposing the extrinsic base below and allowing the metal layer required for silicidation to be deposited thereon. This metal layer can be deposited, for example, using a high pressure sputtering technique to ensure that all exposed surfaces of the extrinsic base, even those below the upper portion of the emitter, are covered.

1 . A transistor comprising:
 an intrinsic base;   an emitter on said intrinsic base, said emitter comprising: a lower portion; and an upper portion above said lower portion;   a dielectric spacer positioned laterally adjacent to said lower portion;   an extrinsic base above said intrinsic base and positioned laterally adjacent to said dielectric spacer opposite said lower portion; and   a silicide layer on said extrinsic base and positioned laterally adjacent to said dielectric spacer opposite said lower portion,   said upper portion being wider than said lower portion and extending laterally over said dielectric spacer and a section of said silicide layer.   
     
     
         2 . The transistor of  claim 1 , further comprising: a dielectric layer on said silicide layer and positioned laterally immediately adjacent to said dielectric spacer opposite said lower portion and further positioned vertically between said section of said silicide layer and said upper portion. 
     
     
         3 . The transistor of  claim 1 , said intrinsic base comprising any one of epitaxial silicon and epitaxial silicon germanium. 
     
     
         4 . A transistor comprising:
 an intrinsic base;   an emitter on said intrinsic base, said emitter comprising: a lower portion; and an upper portion above said lower portion;   a dielectric spacer positioned laterally adjacent to said lower portion;   an extrinsic base above said intrinsic base and positioned laterally adjacent to said dielectric spacer opposite said lower portion; and   a silicide layer on said extrinsic base and positioned laterally adjacent to said dielectric spacer opposite said lower portion,   said upper portion being wider than said lower portion, extending laterally over said dielectric spacer and a section of said silicide layer, and having a top surface and a tapered sidewall, said tapered sidewall tapering from said top surface toward said dielectric spacer such that a width of said upper portion decreases between said top surface and an interface between said upper portion and said lower portion.   
     
     
         5 . The transistor of  claim 4 , further comprising a dielectric layer on said silicide layer and positioned laterally adjacent to said dielectric spacer opposite said lower portion and further positioned vertically between said section of said silicide layer and said tapered sidewall of said upper portion. 
     
     
         6 . The transistor of  claim 4 , said tapered sidewall having a taper angle ranging between 30 and 75 degrees. 
     
     
         7 . The transistor of  claim 4 , said tapered sidewall having a taper angle of approximately 45 degrees. 
     
     
         8 . The transistor of  claim 4 , said tapered sidewall being any one of linear and curved. 
     
     
         9 . The transistor of  claim 4 , said intrinsic base comprising any one of epitaxial silicon and epitaxial silicon germanium. 
     
     
         10 . A heterojunction bipolar transistor comprising:
 an intrinsic base comprising epitaxial silicon germanium;   an emitter on said intrinsic base, said emitter comprising: a lower portion; and an upper portion above said lower portion;   a dielectric spacer positioned laterally adjacent to said lower portion;   an extrinsic base above said intrinsic base and positioned laterally adjacent to said dielectric spacer opposite said lower portion; and   a silicide layer on said extrinsic base and positioned laterally adjacent to said dielectric spacer opposite said lower portion,   said upper portion being wider than said lower portion, extending laterally over said dielectric spacer and a section of said silicide layer, and having a top surface and a tapered sidewall, said tapered sidewall tapering from said top surface toward said dielectric spacer such that a width of said upper portion decreases between said top surface and an interface between said upper portion and said lower portion.   
     
     
         11 . The transistor of  claim 10 , further comprising a dielectric layer on said silicide layer and positioned laterally adjacent to said dielectric spacer opposite said lower portion and further positioned vertically between said section of said silicide layer and said tapered sidewall of said upper portion. 
     
     
         12 . The transistor of  claim 10 , said tapered sidewall having a taper angle ranging between 30 and 75 degrees. 
     
     
         13 . The transistor of  claim 10 , said tapered sidewall having a taper angle of approximately 45 degrees. 
     
     
         14 . The transistor of  claim 10 , said tapered sidewall being any one of linear and curved. 
     
     
         15 . A method of forming a transistor, said method comprising:
 performing at least one etch process so as to create, from a polysilicon layer, an emitter comprising: a lower portion and an upper portion above said lower portion, said lower portion being on an intrinsic base and positioned laterally adjacent to a dielectric spacer and said upper portion being wider than said lower portion and extending laterally over said dielectric spacer onto a sacrificial layer;   selectively removing said sacrificial layer so as to expose an extrinsic base on said intrinsic base and positioned laterally adjacent to said dielectric spacer opposite said lower portion; and   forming a silicide layer on said extrinsic base such that said silicide layer is positioned laterally adjacent to said dielectric spacer opposite said lower portion and such that a section of said silicide layer is below said upper portion.   
     
     
         16 . The method of  claim 15 , said forming of said silicide layer comprising:
 sputtering a metal layer onto said extrinsic base in order to ensure that said metal layer is deposited below said upper portion of said emitter, said sputtering being performed at a pressure of at least 20 mTorr and with a radio frequency (RF) bias of at least 5 Watts; and   performing a silicidation anneal.   
     
     
         17 . The method of  claim 15 , further comprising forming a dielectric layer on said silicide layer such that said dielectric layer is positioned laterally adjacent to said dielectric spacer opposite said lower portion and further positioned vertically between said section of said silicide layer and said tapered sidewall of said upper portion. 
     
     
         18 . The method of  claim 15 , said forming of said intrinsic base comprising epitaxially growing, on a silicon substrate, any one of silicon layer and a silicon germanium layer. 
     
     
         19 . A method of forming a bipolar transistor, said method comprising:
 performing at least one etch process so as to create, from a polysilicon layer, an emitter comprising: a lower portion and an upper portion above said lower portion,
 said lower portion being on an intrinsic base and positioned laterally adjacent to a dielectric spacer, and 
 said upper portion being wider than said lower portion, extending laterally over said dielectric spacer onto a sacrificial layer and having a tapered sidewall, said tapered sidewall tapering from a top surface of said upper portion toward said dielectric spacer such that a width of said upper portion decreases between said top surface and an interface between said upper portion and said lower portion; 
   selectively removing said sacrificial layer so as to expose an extrinsic base on said intrinsic base and positioned laterally adjacent to said dielectric spacer opposite said lower portion; and   forming a silicide layer on said extrinsic base such that said silicide layer is positioned laterally adjacent to said dielectric spacer opposite said lower portion and such that a section of said silicide layer is below said upper portion.   
     
     
         20 . The method of  claim 19 , said forming of said silicide layer comprising:
 sputtering a metal layer onto said extrinsic base in order to ensure that said metal layer is deposited below said upper portion of said emitter, said sputtering being performed at a pressure of at least 20 mTorr and with a radio frequency (RF) bias of at least 5 Watts; and   performing a silicidation anneal.   
     
     
         21 . The method of  claim 19 , said performing of said at least one etch process comprising performing said at least one etch process such that said tapered sidewall has a taper angle ranging between 30 and 75 degrees. 
     
     
         22 . The method of  claim 19 , said performing of said at least one etch process comprising performing said at least one etch process such that said tapered sidewall has a taper angle of approximately 45 degrees. 
     
     
         23 . The method of  claim 19 , said performing of said at least one etch process comprising performing said at least one etch process such that said tapered sidewall is any one of linear and curved. 
     
     
         24 . The method of  claim 19 , further comprising forming a dielectric layer on said silicide layer such that said dielectric layer is positioned laterally adjacent to said dielectric spacer opposite said lower portion and further positioned vertically between said section of said silicide layer and said tapered sidewall of said upper portion. 
     
     
         25 . The method of  claim 19 , said forming of said intrinsic base comprising epitaxially growing, on a silicon substrate, any one of silicon layer and a silicon germanium layer.