Semiconductor Device Having A Modified Shallow Trench Isolation (STI) Region And A Modified Well Region

Abstract

An apparatus is disclosed to increase a breakdown voltage of a semiconductor device. The semiconductor device can include a modified breakdown shallow trench isolation (STI) region to effectively reduce its drain to source resistance when compared to a conventional semiconductor device. This reduction in the drain to source resistance increases the breakdown voltage of the semiconductor device when compared to the conventional semiconductor device by allowing more current to pass from a source region to a drain region of the semiconductor device. The semiconductor device can include a modified well region to reduce its drain to source resistance. The modified well region allows more current to pass from a source region to a drain region of the semiconductor device, thereby further increasing the break down voltage of the semiconductor device from that of the conventional semiconductor device.

1 . A metal oxide semiconductor (MOS) device, comprising:
 a source region;   a drain region;   a gate region configured to be positioned between the source region and the drain region,   a shallow trench isolation (STI) region configured to be positioned between the drain region and the gate region,   a well region configured to be positioned between the drain region and the gate region, the well region including a first well region and a second well region, the second well region being heavily doped relative to the first well region and being configured to be positioned between the STI region and the first well region; and   a gate oxide region configured to be positioned beneath the gate region, the gate oxide region being configured to be in contact with the first and the second well regions.   
     
     
         2 . The MOS device of  claim 1 , wherein the STI region comprises:
 a top edge;   a bottom edge;   a first slanted edge; and   a second slanted edge,   wherein the top edge, the bottom edge, the first slanted edge, and the second slanted edge are configured and arranged to form a quadrilateral.   
     
     
         3 . The MOS device of  claim 2 , wherein the first and the second well regions are configured to contact the first slanted edge. 
     
     
         4 . The MOS device of  claim 3 , wherein the first well region is configured to contact the bottom edge and the second slanted edge. 
     
     
         5 . The MOS device of  claim 4 , wherein the first well region is configured to contact the drain region. 
     
     
         6 . The MOS device of  claim 1 , wherein the well region further includes a third well region, the third well region being lightly doped relative to the second well region. 
     
     
         7 . A metal oxide semiconductor (MOS) device, comprising:
 a first region configured to form a source region of the MOS device;   a second region configured to form a drain region of the MOS device;   a third region, positioned between the source region and the drain region, configured to form a gate region of the MOS device; and   a fourth region, positioned between the drain region and the gate region, configured to form a shallow trench isolation (STI) region of the MOS device, the STI region being characterized as having a plurality of sides;   a fifth region, positioned between the gate region and the drain region configured to form a first well region of the MOS device, the first well region being configured to contact more than one side from among the plurality of sides; and   a sixth region, positioned between the gate region and the STI region configured to form a second well region of the MOS device, the second well region being heavily doped relative to the first well region and being configured to contact at least one side from among the plurality of sides.   
     
     
         8 . The MOS device of  claim 7 , wherein the plurality of sides comprises:
 a top edge;   a bottom edge;   a first slanted edge; and   a second slanted edge,   wherein the top edge, the bottom edge, and the first and the second slanted edges are configured and arranged to form a quadrilateral, and   wherein the first well region and the second well region are configured to contact the first slanted edge.   
     
     
         9 . The MOS device of  claim 8 , wherein the first well region is configured to contact the top edge and the second slanted edge. 
     
     
         10 . The MOS device of  claim 9 , wherein the first well region is configured to contact the drain region. 
     
     
         11 . The MOS device of  claim 7 , further comprising:
 a gate oxide region configured to be positioned beneath the gate region, the gate oxide region being configured to be in contact with the first and the second well regions.   
     
     
         12 . The MOS device of  claim 7 , further comprising:
 a seventh region, positioned between the gate region and the second well region, configured to form a third well region of the MOS device, the third well region being lightly doped relative to the second well region.   
     
     
         13 . The MOS device of  claim 12 , wherein the first, the second, and the third well regions are configured to contact one another. 
     
     
         14 . The MOS device of  claim 12 , wherein the third well region is configured to not contact the drain region. 
     
     
         15 . A laterally diffused metal oxide semiconductor (LDMOS) device, comprising:
 a source region;   a gate region;   a drain region configured to be laterally displaced from the gate region;   a shallow trench isolation (STI) region configured to be positioned between the drain region and the gate region,   a well region configured to be positioned between the drain region and the gate region, the well region including a first well region and a second well region, the second well region being heavily doped relative to the first well region; and   a gate oxide region configured to be positioned beneath the gate region, the gate oxide region being in contact with the first and the second well regions.   
     
     
         16 . The LDMOS device of  claim 15 , wherein the STI region comprises:
 a top edge;   a bottom edge;   a first slanted edge; and   a second slanted edge,   wherein the top edge, the bottom edge, and the first and the second slanted edges are configured and arranged to form a quadrilateral.   
     
     
         17 . The LDMOS device of  claim 16 , wherein the first and the second well regions are configured to contact the first slanted edge. 
     
     
         18 . The LDMOS device of  claim 17 , wherein the first well region is configured to contact the bottom edge and the second slanted edge. 
     
     
         19 . The LDMOS device of  claim 18 , wherein the first well region is configured to contact the drain region. 
     
     
         20 . The LDMOS device of  claim 15 , wherein the well region further includes a third well region, the third well region being lightly doped relative to the second well region.