Equalizer with Controllably Weighted Parallel High Pass and Low Pass Filters and Receiver Including Such an Equalizer

Abstract

An adjustable equalizer that includes a first branch including a low pass filter (LPF) typically having a variable gain (β), and a second branch including a high pass filter (HPF) typically having another variable gain (α). Outputs of the branches in response to an input signal are summed to produce an equalized output. The equalizer can be implemented using CMOS technology and can be capable of equalizing an input indicative of data having a maximum data rate of at least 1 Gb/s. Typically, the equalizer is embodied in a receiver for use in equalizing a signal, indicative of video or other data, that has propagated over a serial link to the receiver.

1 . An equalizer, comprising:
 a first branch configured to realize a low pass filter and having a variable first gain, wherein the first branch is configured to low-pass filter an input signal and apply the first gain to the input signal;   a second branch configured to realize a high pass filter and having a variable second gain, wherein the second branch is configured to high-pass filter the input signal and apply the second gain to the input signal;   at least one input node, from which the input signal is asserted to the first branch and the second branch; and   at least one output node, common to both the first branch and the second branch, at which the equalizer asserts an equalized signal in response to the input signal, wherein the equalizer has a transfer function having a zero whose location can be controlled by varying one of the first gain and the second gain relative to the other of said first gain and said second gain.   
     
     
         2 . The equalizer of  claim 1 , wherein the first branch and the second branch include at least some circuitry common to both said first branch and said second branch. 
     
     
         3 . The equalizer of  claim 1 , wherein the first gain and the second gain are independently controllable. 
     
     
         4 . The equalizer of  claim 1 , wherein each of the first gain and the second gain is based on at least one of a channel characteristic, a transmitter characteristic, and a receiver characteristic. 
     
     
         5 . The equalizer of  claim 1 , wherein said equalizer is implemented in a receiver to which the input signal has propagated over a link, the input signal is indicative of data, the equalized signal is indicative of the data, and the receiver includes additional circuitry coupled and configured to recover the data from the equalized signal. 
     
     
         6 . The equalizer of  claim 1 , wherein the transfer function has a peak-to-DC gain difference that can be controlled by varying one of the first gain and the second gain relative to the other of said first gain and said second gain. 
     
     
         7 . The equalizer of  claim 1 , wherein each of the input signal and the equalized signal is a differential signal, and the at least one output node is a pair of nodes at which the equalizer asserts components of the equalized signal. 
     
     
         8 . The equalizer of  claim 1 , wherein the equalizer is implemented using CMOS technology. 
     
     
         9 . The equalizer of  claim 1 , wherein the input signal is indicative of data having a maximum data rate of at least 1 Gb/s, and the equalizer is implemented using CMOS technology. 
     
     
         10 . The equalizer of  claim 1 , wherein each of the input signal and the equalized signal is a differential signal, the first branch includes a first differential pair, the second branch includes a second differential pair, the first differential pair includes a first MOS transistor and a second MOS transistor, the second differential pair includes a third MOS transistor and a fourth MOS transistor, a gate of each of the first MOS transistor and the fourth MOS transistor is coupled to receive a first component of the input signal, a gate of each of the second MOS transistor and the third MOS transistor is coupled to receive a second component of the input signal, current flows from a first current sharing node through the first MOS transistor and the fourth MOS transistor during operation of the equalizer, and current flows from a second current sharing node through the second MOS transistor and the third MOS transistor during operation of the equalizer. 
     
     
         11 . The equalizer of  claim 10 , wherein the first differential pair includes a first controllable current source coupled to sink a variable first tail current that determines the first gain, and the second differential pair includes a second controllable current source coupled to sink a variable second tail current that determines the second gain. 
     
     
         12 . An equalizer implemented using CMOS technology, comprising:
 a first branch configured to realize a low pass filter, wherein the first branch is configured to low-pass filter an input signal;   a second branch configured to realize a high pass filter, wherein the second branch is configured to high-pass filter the input signal;   at least one input node, from which the input signal is asserted to the first branch and the second branch; and   at least one output node, common to both the first branch and the second branch, at which the equalizer asserts an equalized signal in response to the input signal.   
     
     
         13 . The equalizer of  claim 12 , wherein the first branch and the second branch include at least some circuitry common to both said first branch and said second branch. 
     
     
         14 . The equalizer of  claim 12 , wherein the first branch has a variable first gain, the first branch is configured to low-pass filter the input signal and apply the first gain to the input signal, the second branch has a variable second gain, the second branch is configured to high-pass filter the input signal and apply the second gain to the input signal, and the first gain and the second gain are independently controllable. 
     
     
         15 . The equalizer of  claim 12 , wherein the first branch is configured to low-pass filter the input signal and apply a first gain to the input signal, the second branch is configured to high-pass filter the input signal and apply a second gain to the input signal, and each of the first gain and the second gain is based on at least one of a channel characteristic, a transmitter characteristic, and a receiver characteristic. 
     
     
         16 . The equalizer of  claim 12 , wherein said equalizer is implemented in a receiver to which the input signal has propagated over a link, the input signal is indicative of data, the equalized signal is indicative of the data, and the receiver includes additional circuitry coupled and configured to recover the data from the equalized signal. 
     
     
         17 . The equalizer of  claim 14 , wherein the equalizer has a transfer function having a zero whose location can be controlled by varying one of the first gain and the second gain relative to the other of said first gain and said second gain. 
     
     
         18 . The equalizer of  claim 17 , wherein the transfer function has a peak-to-DC gain difference that can be controlled by varying one of the first gain and the second gain relative to the other of said first gain and said second gain. 
     
     
         19 . The equalizer of  claim 12 , wherein each of the input signal and the equalized signal is a differential signal, and the at least one output node is a pair of nodes at which the equalizer asserts components of the equalized signal. 
     
     
         20 . The equalizer of  claim 12 , wherein the input signal is indicative of data having a maximum data rate of at least 1 Gb/s. 
     
     
         21 . The equalizer of  claim 12 , wherein each of the input signal and the equalized signal is a differential signal, the first branch includes a first differential pair, the second branch includes a second differential pair, the first differential pair includes a first MOS transistor and a second MOS transistor, the second differential pair includes a third MOS transistor and a fourth MOS transistor, a gate of each of the first MOS transistor and the fourth MOS transistor is coupled to receive a first component of the input signal, a gate of each of the second MOS transistor and the third MOS transistor is coupled to receive a second component of the input signal, current flows from a first current sharing node through the first MOS transistor and the fourth MOS transistor during operation of the equalizer, and current flows from a second current sharing node through the second MOS transistor and the third MOS transistor during operation of the equalizer. 
     
     
         22 . The equalizer of  claim 21 , wherein the first differential pair includes a first controllable current source coupled to sink a variable first tail current that determines the first gain, and the second differential pair includes a second controllable current source coupled to sink a variable second tail current that determines the second gain. 
     
     
         23 . An equalizer implemented using CMOS technology, comprising:
 a first branch configured to realize a low pass filter;   a second branch configured to realize a high pass filter;   at least one input node, from which an input signal is asserted to the first branch and the second branch; and   at least one output node, common to both the first branch and the second branch, at which the equalizer asserts an equalized signal in response to the input signal.   
     
     
         24 . The equalizer of  claim 23 , wherein the first branch and the second branch include at least some circuitry common to both said first branch and said second branch. 
     
     
         25 . The equalizer of  claim 23 , wherein said equalizer is implemented in a receiver to which the input signal has propagated over a link, the input signal is indicative of data, the equalized signal is indicative of the data, and the receiver includes additional circuitry coupled and configured to recover the data from the equalized signal, 
     
     
         26 . The equalizer of  claim 23 , wherein each of the input signal and the equalized signal is a differential signal, and the at least one output node is a pair of nodes at which the equalizer asserts components of the equalized signal. 
     
     
         27 . The equalizer of  claim 23 , wherein the input signal is indicative of data having a maximum data rate of at least 1 Gb/s. 
     
     
         28 . The equalizer of  claim 23 , wherein each of the input signal and the equalized signal is a differential signal, the first branch includes a first differential pair, the second branch includes a second differential pair, the first differential pair includes a first MOS transistor and a second MOS transistor, the second differential pair includes a third MOS transistor and a fourth MOS transistor, a gate of each of the first MOS transistor and the fourth MOS transistor is coupled to receive a first component of the input signal, a gate of each of the second MOS transistor and the third MOS transistor is coupled to receive a second component of the input signal, current flows from a first current sharing node through the first MOS transistor and the fourth MOS transistor during operation of the equalizer, and current flows from a second current sharing node through the second MOS transistor and the third MOS transistor during operation of the equalizer. 
     
     
         29 . The equalizer of  claim 28 , wherein the first differential pair includes a first controllable current source coupled to sink a variable first tail current that determines a variable first gain, and the second differential pair includes a second controllable current source coupled to sink a variable second tail current that determines a variable second gain. 
     
     
         30 . The equalizer of  claim 29 , wherein the equalizer has a transfer function having a zero whose location can be controlled by controlling one or both of the first controllable current source and the second controllable current source to vary one of the first tail current and the second tail current relative to the other of the first tail current and the second tail current.