Metal semiconductor alloy structure for low contact resistance

Abstract

Contact via holes are etched in a dielectric material layer overlying a semiconductor layer to expose the topmost surface of the semiconductor layer. The contact via holes are extended into the semiconductor material layer by continuing to etch the semiconductor layer so that a trench having semiconductor sidewalls is formed in the semiconductor material layer. A metal layer is deposited over the dielectric material layer and the sidewalls and bottom surface of the trench. Upon an anneal at an elevated temperature, a metal semiconductor alloy region is formed, which includes a top metal semiconductor alloy portion that includes a cavity therein and a bottom metal semiconductor alloy portion that underlies the cavity and including a horizontal portion. A metal contact via is formed within the cavity so that the top metal semiconductor alloy portion laterally surrounds a bottom portion of a bottom portion of the metal contact via.

1 . A semiconductor structure comprising:
 a trench located in a semiconductor material region in a semiconductor substrate;   a metal semiconductor alloy region located within said trench; and   a contact via structure including a lower contact via portion that is located within said metal semiconductor alloy region and laterally spaced from said semiconductor material region by said metal semiconductor alloy region.   
     
     
         2 . The semiconductor structure of  claim 1 , wherein an entirety of said metal semiconductor alloy region is of integral construction and includes an upper metal semiconductor alloy portion and a lower metal semiconductor alloy portion, wherein said upper metal semiconductor alloy portion laterally surrounds said lower contact via portion and said lower metal semiconductor alloy portion underlies said lower contact via portion. 
     
     
         3 . The semiconductor structure of  claim 2 , wherein an inner sidewall and an outer sidewall of said upper metal semiconductor alloy portion are laterally spaced by a substantially constant width throughout an entirety of a periphery of said lower contact via portion. 
     
     
         4 . The semiconductor structure of  claim 2 , wherein said lower metal semiconductor alloy portion has a constant thickness between an upper horizontal surface of said lower metal semiconductor alloy portion and a lower horizontal surface of said lower metal semiconductor alloy portion. 
     
     
         5 . The semiconductor structure of  claim 1 , wherein a sidewall of an upper portion of said contact via structure contacts said metal semiconductor alloy region between an uppermost portion of an inner sidewall of said metal semiconductor alloy region and an uppermost portion of an outer sidewall of said metal semiconductor alloy region. 
     
     
         6 . The semiconductor structure of  claim 1 , further comprising at least one dielectric material layer overlying said semiconductor substrate, wherein an upper contact via portion of said contact via structure is embedded in said at least one dielectric material layer. 
     
     
         7 . The semiconductor structure of  claim 6 , wherein said semiconductor material region and said metal semiconductor alloy region contact said at least one dielectric material layer. 
     
     
         8 . The semiconductor structure of  claim 6 , wherein a topmost surface of said upper contact via portion is coplanar with a topmost surface of said at least one dielectric layer. 
     
     
         9 . The semiconductor structure of  claim 1 , further comprising:
 another trench located in another semiconductor material region in said semiconductor substrate; and   another metal semiconductor alloy region located within said other trench, wherein said contact via structure contiguously extends from a surface of said metal semiconductor alloy region to a surface of said other metal semiconductor alloy region.   
     
     
         10 . The semiconductor structure of  claim 9 , further comprising a shallow trench isolation structure contacting a bottom surface of said contact via structure. 
     
     
         11 . The semiconductor structure of  claim 6 , wherein an entirety of a periphery of said upper contact via portion contacts an upper surface of said metal semiconductor alloy region. 
     
     
         12 . The semiconductor structure of  claim 1 , wherein said lower contact via portion extends below a planar top surface of said semiconductor substrate. 
     
     
         13 . The semiconductor structure of  claim 12 , wherein said planar top surface of said semiconductor substrate is substantially coplanar with an interface between a gate dielectric and a semiconductor portion within said semiconductor substrate. 
     
     
         14 . The semiconductor structure of  claim 1 , wherein said semiconductor material region is a source region or a drain region of a field effect transistor. 
     
     
         15 . The semiconductor structure of  claim 14 , wherein a lower metal semiconductor alloy portion of said metal semiconductor alloy region is located between a horizontal plane that includes a bottom surface of a gate dielectric and a bottommost surface of said source region or said drain region. 
     
     
         16 . The semiconductor structure of  claim 1 , wherein said contact via structure directly contacts a surface of said semiconductor material region. 
     
     
         17 . A method of forming a semiconductor structure comprising:
 forming at least one dielectric material layer over a semiconductor structure including a semiconductor material region;   forming a trench that extends from a top surface of said at least one dielectric material layer into said semiconductor material portion; and   forming a metal semiconductor alloy region by diffusing a metal into said semiconductor material region through a sidewall of said trench.   
     
     
         18 . The method of  claim 17 , further comprising forming a contact via structure on said metal semiconductor alloy region by filling said trench with a conductive material. 
     
     
         19 . The method of  claim 17 , wherein an entirety of said metal semiconductor alloy region is formed as a structure of integral construction and includes an upper metal semiconductor alloy portion and a lower metal semiconductor alloy portion, wherein said lower contact via portion is laterally surrounded by said upper metal semiconductor alloy portion and overlies and said lower metal semiconductor alloy portion upon formation. 
     
     
         20 . The method of  claim 16 , wherein said metal semiconductor alloy region is formed by deposition of a metal layer on a sidewall and a bottom surface of said trench, interdiffusion of said metal and a semiconductor material of said semiconductor material region, and removal of an unreacted portion of said metal layer.